View CYP15G0403DXB-BGC_3290010.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary independent clock quad hotlink ii ? transceive r cyp15g0403dxb cyv15g0403dxb cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-02065 rev. *c revised june 11, 2004 features ? quad channel transceiver for 195- to 1500-mbaud serial signaling rate aggregate throughput of up to 12 gbits/second ? second-generation hotlink ? technology ? compliant to multiple standards escon, dvb-asi, smpte-292m, smpte-259m, fibre channel and gigabit ethernet (ieee802.3z) 8b/10b coded data or 10 bit uncoded data ? truly independent channels each channel can operate at a different signaling rate each channel can transport a different type of data ? selectable input/output clocking options ? internal phase-locked loops (plls) with no external pll components ? dual differential pecl-compatible serial inputs per channel internal dc-restoration ? dual differential pecl-compatible serial outputs per channel source matched for 50 transmission lines no external bias resistors required signaling-rate controlled edge-rates ? multiframe ? receive framer provides alignment options bit and byte alignment comma or full k28.5 detect single or multi-byte framer for byte alignment low-latency option ? synchronous lvttl parallel interface ? jtag boundary scan ? built-in self-test (bist) for at-speed link testing ? compatible with fiber-optic modules copper cables circuit board traces ? per-channel link quality indicator analog signal detect digital signal detect ? low-power 3w @ 3.3v typical ? single 3.3v supply ? 256-ball thermally enhanced bga ? 0.25 bicmos technology functional description the cyp(v)15g0403dxb [1] independent clock quad hotlinkii ? transceiver is a point-to-point or point-to-multi- point communications building block enabling transfer of data over a variety of high-speed serial links like optical fiber, balanced, and unbalanced copper transmission lines. the signaling rate can be anywhere in the range of 195 to 1500 mbaud per serial link. each channel operates independently with its own reference clock allowing different rates. each transmit channel accepts parallel characters in an input register, encodes each character for transport, and then converts it to serial data. each receive channel accepts serial data and converts it to parallel data, decodes the data into characters, and presents these characters to an output register. figure1 illustrates typical connections between independent host systems and corresponding cyp(v)15g0403dxb chips. note: 1.cyv15g0403dxb refers to the smpte-compliant devices. cyp15g0403dxb refers to the non-smpte devices. cyp(v)15g0403dxb corresponds to both smpte and non-smpte devices. figure 1. hotlink ii ? system connections serial links 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 serial links serial links serial links backplane or cabled connections independent cyp(v)15g0403dxbcyp(v)15g0403dxb independent
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 2 of 43 the cyv15g0403dxb satisfies the smpte-259m and smpte-292m compliance as per smpte eg34-1999 patho- logical test requirements. as a second-generation hotlink device, the cyp(v)15g0403dxb extends the hotlink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility (data, command, and bist) with other hotlink devices. the transmit (tx) section of the cyp(v)15g0403dxb quad hotlink ii consists of four independent byte-wide channels. each channel can accept either 8-bit data characters or preencoded 10-bit transmission characters. data characters may be passed from the transmit input register to an integrated 8b/10b encoder to improve their serial transmission characteristics. these encoded characters are then serialized and output from dual positive ecl (pecl) compatible differential transmission-line drivers at a bit-rate of either 10- or 20-times the input reference clock for that channel. the receive (rx) section of the cyp(v)15g0403dxb quad hotlink ii consists of four independent byte-wide channels. each channel accepts a serial bit-stream from one of two pecl-compatible differential line receivers, and using a completely integrated clock and data recovery pll, recovers the timing information necessary for data reconstruction. each recovered bit-stream is deserialized and framed into characters, 8b/10b decoded, and checked for transmission errors. recovered decoded characters are then written to an internal elasticity buffer, and presented to the destination host system. the integrated 8b/10b encoder/decoder may be bypassed for systems that present externally encoded or scrambled data at the parallel interface. the parallel i/o interface may be configured for numerous forms of clocking to provide the highest flexibility in system architecture. in addition to clocking the transmit path with a local reference clock, the receive interface may also be configured to present data relative to a recovered clock or to a local reference clock. each transmit and receive channel contains an independent bist pattern generator and checker. this bist hardware allows at-speed testing of the high-speed serial data paths in each transmit and receive section, and across the intercon- necting links. the cyp(v)15g0403dxb is ideal for port applications where different data rates and serial interface standards are necessary for each channel. some applications include multi- protocol routers, aggregation equipment, and switches. cyp(v)15g0403dxb transceiver logic block diagram x10 serializer phase encoder 8b/10b decoder 8b/10b x11 framer deserializer tx rx x10 serializer encoder 8b/10b decoder 8b/10b x11 framer deserializer tx rx x10 serializer encoder 8b/10b decoder 8b/10b x11 framer deserializer tx rx x10 serializer encoder 8b/10b decoder 8b/10b x11 framer deserializer tx rx t x d a [ 7 : 0 ] r x d a [ 7 : 0 ] t x d b [ 7 : 0 ] r x d b [ 7 : 0 ] t x d c [ 7 : 0 ] r x d c [ 7 : 0 ] t x d d [ 7 : 0 ] r x d d [ 7 : 0 ] o u t a 1 o u t a 2 i n a 1 i n a 2 o u t b 1 o u t b 2 i n b 1 i n b 2 o u t c 1 o u t c 2 i n c 1 i n c 2 o u t d 1 o u t d 2 i n d 1 i n d 2 align buffer phase align buffer phase align buffer phase align buffer elasticity buffer elasticity buffer elasticity buffer elasticity buffer t x c t a [ 1 : 0 ] r x s t a [ 2 : 0 ] t x c t b [ 1 : 0 ] r x s t b [ 2 : 0 ] t x c t c [ 1 : 0 ] r x s t c [ 2 : 0 ] t x c t d [ 1 : 0 ] r x s t d [ 2 : 0 ]
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 3 of 43 txlba txlbc transmit path block diagram txratea spdsela refclka+ refclka C transmit pll clock multiplier txclka bit-rate clock character-rate clock a outa1+ outa1 C outa2+ outa2 C 8 txrateb spdselb refclkb+ refclkb C bit-rate clock character-rate clock b outb1+ outb1 C outb2+ outb2 C transmit pll clock multiplier a txclkb txratec spdselc refclkc+ refclkc C txclkc bit-rate clock character-rate clock c txrated spdseld refclkd+ refclkd C transmit pll clock multiplier d txclkd bit-rate clock character-rate clock d outd1+ outd1 C outd2+ outd2 C outc1+ outc1 C outc2+ outc2 C txcta[1:0] txdd[7:0] oea[2..1] txbist encbypa txcksela = internal signal txerra txerrb txerrd txerrc txclkoa txclkob txclkoc txclkod txda[7:0] 2 txdb[7:0] 8 2 txctb[1:0] 8 2 txdc[7:0] txctc[1:0] 8 2 txctd[1:0] 10 10 10 10 10101010 10 10 1010 1010 10 10 a encbypb encbypc encbypd txbist b txbist c txbistd oeb[2..1] oec[2..1] oed[2..1] pabrsta pabrstb pabrstc pabrstd oea[2..1] oeb[2..1] oec[2..1] oed[2..1] txlbd txlbb transmit pll clock multiplier b transmit pll clock multiplier c 1 0 txckselb 0 txckselc 1 0 txckseld 1 0 txlb[a..d] are internal serial loopback signals 1
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 4 of 43 ina1+ ina1 C ina2+ ina2 C insela inb1+ inb1 C inb2+ inb2 C inselb inc1+ inc1 C inc2+ inc2 C inselc ind1+ ind1 C ind2+ ind2 C inseld clock & data recovery pll clock & data recovery pll clock & data recovery pll clock & data recovery pll lfid lfic lfib lfia 8 rxstc[2:0] rxdc[7:0] 3 8 rxstb[2:0] rxdb[7:0] 3 8 rxstd[2:0] rxdd[7:0] 3 8 rxsta[2:0] rxda[7:0] 3 receive signal monitor receive signal monitor receive signal monitor receive signal monitor rxclkd+ rxclkd C 2 rxclkc+ rxclkc C 2 rxclkb+ rxclkb C 2 rxclka+ rxclka C 2 rxrate[a..d] framchar[a..d] rfen[a..d] sdasela[1:0] jtag boundary scan controller tdo tms tclk tdi clock select clock select clock select clock select rxcksel[a..d] reset receive path block diagram =internal signal rxpllpda rfmode[a..d][1:0] lpena rxbist[a..d] decmode[a..d] lpenb lpenc lpend trst sdaselb[1:0] rxpllpdb sdaselc[1:0] rxpllpdc sdaseld[1:0] rxpllpdd decbyp[a..d] spdsela spdselb spdselc spdseld ulcb ulca ulcc ulcd ldtden txlbd txlbc txlbb txlba txlb[a..d] are internal serial loopback signals
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 5 of 43 pin configuration (top view) wren addr[3:0] data[7:0] device configuration and control block diagram = internal signal rxrate[a..d] framchar[a..d] rfen[a..d] rxcksel[a..d] rfmode[a..d][1:0] rxbist[a..d] decmode[a..d] decbyp[a..d] sdasel[2..1][a..d][1:0] rxpllpd[a..d] txrate[a..d] txcksel[a..d] txbist[a..d] oe[2..1][a..d] pabrst[a..d] encbyp[a..d] glen[11..0] fglen[2..0] device configuration and control interface 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a in c1 C out c1 C in c2 C out c2 C v cc in d1 C out d1 C gnd in d2 C out d2 C in a1 C out a1 C gnd in a2 C out a2 C v cc in b1 C out b1 C in b2 C out b2 C b in c1+ out c1+ in c2+ out c2+ v cc in d1+ out d1+ gnd in d2+ out d2+ in a1+ out a1+ gnd in a2+ out a2+ v cc in b1+ out b1+ in b2+ out b2+ c tditmsinselcinselb v cc ulcd ulcc gnd data [7] data [5] data [3] data [1] gnd ncspd seld v cc ldtd en trst lpendtdo d tclkreset inseldinsela v cc ulca spd selc gnd data [6] data [4] data [2] data [0] gnd lpenbulcb v cc lpenalten1scan en2 tmen3 e v cc v cc v cc v cc v cc v cc v cc v cc f rx dc[6] rx dc[7] tx dc[0] nc nc rx stb[1] tx clkob rx stb[0] g tx dc[7]wren tx dc[4] tx dc[1] spd selb lp enc spd sela rx db[1] h gndgndgndgnd gndgndgndgnd j tx ctc[1] tx dc[5] tx dc[2] tx dc[3] rx stb[2] rx db[0] rx db[5] rx db[2] k rx dc[2] ref clkc C tx ctc[0] tx clkc rx db[3] rx db[4] rx db[7]lfib l rx dc[3] ref clkc+ lfic tx dc[6] rx db[6] rx clkb+ rx clkb C tx db[6] m rx dc[4] rx dc[5] nc tx errc ref clkb+ ref clkb C tx errb tx clkb n gndgndgndgnd gndgndgndgnd p rx dc[1] rx dc[0] rx stc[0] rx stc[1] tx db[5] tx db[4] tx db[3] tx db[2] r rx stc[2] tx clkoc rx clkc+ rx clkc C tx db[1] tx db[0] tx ctb[1] tx db[7] t v cc v cc v cc v cc v cc v cc v cc v cc u tx dd[0] tx dd[1] tx dd[2] tx ctd[1] v cc rx dd[2] rx dd[1] gnd tx cta[1] addr [0] ref clkd C tx da[1] gnd tx da[4] tx cta[0] v cc rx da[2] tx ctb[0] rx sta[2] rx sta[1] v tx dd[3] tx dd[4] tx ctd[0] rx dd[6] v cc rx dd[3] rx std[0] gnd rx std[2] addr [2] ref clkd+ tx clkoa gnd tx da[3] tx da[7] v cc rx da[7] rx da[3] rx da[0] rx sta[0] w tx dd[5] tx dd[7] lfid rx clkd C v cc rx dd[4] rx std[1] gnd addr [3] addr [1] rx clka+ tx erra gnd tx da[2] tx da[6] v cc lfia ref clka+ rx da[4] rx da[1] y tx dd[6] tx clkd rx dd[7] rx clkd+ v cc rx dd[5] rx dd[0] gnd tx clkod nc tx clka rx clka C gnd tx da[0] tx da[5] v cc tx errd ref clka C rx da[6] rx da[5]
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 6 of 43 pin configuration (bottom view) 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a out b2 C in b2 C out b1 C in b1 C v cc out a2 C in a2 C gnd out a1 C in a1 C out d2 C in d2 C gnd out d1 C in d1 C v cc out c2 C in c2 C out c1 C in c1 C b out b2+ in b2+ out b1+ in b1+ v cc out a2+ in a2+ gnd out a1+ in a1+ out d2+ in d2+ gnd out d1+ in d1+ v cc out c2+ in 2+ out c1+ in c1+ c tdo lp end trst ldtd en v cc spd seld nc gnd data [1] data [3] data [5] data [7] gnd ulcc ulcd v cc in selb in selc tmstdi d tmen3scan en2 lten1lp ena v cc ulcb lp enb gnd data [0] data [2] data [4] data [6] gnd spd selc ulca v cc in sela in seld reset tclk e v cc v cc v cc v cc v cc v cc v cc v cc f rx stb[0] tx clkob rx stb[1] nc nc tx dc[0] rx dc[7] rx dc[6] g rx db[1] spd sela lp enc spd selb tx dc[1] tx dc[4] wren tx dc[7] h gndgndgndgnd gndgndgndgnd j rx db[2] rx db[5] rx db[0] rx stb[2] tx dc[3] tx dc[2] tx dc[5] tx ctc[1] k lfib rx db[7] rx db[4] rx db[3] tx clkc tx ctc[0] ref clkc C rx dc[2] l tx db[6] rx clkb C rx clkb+ rx db[6] tx dc[6] lfic ref clkc+ rx dc[3] m tx clkb tx errb ref clkb C ref clkb+ tx errc nc rx dc[5] rx dc[4] n gndgndgndgnd gndgndgndgnd p tx db[2] tx db[3] tx db[4] tx db[5] rx stc[1] rx stc[0] rx dc[0] rx dc[1] r tx db[7] tx ctb[1] tx db[0] tx db[1] rx clkc C rx clkc+ tx clkoc rx stc[2] t v cc v cc v cc v cc v cc v cc v cc v cc u rx sta[1] rx sta[2] tx ctb[0] rx da[2] v cc tx cta[0] tx da[4] gnd tx da[1] ref clkd C addr [0] txc ta[1] gnd rx dd[1] rx dd[2] v cc tx ctd[1] tx dd[2] tx dd[1] tx dd[0] v rx sta[0] rx da[0] rx da[3] rx da[7] v cc tx da[7] tx da[3] gnd tx clkoa ref clkd+ addr [2] rx std[2] gnd rx std[0] rx dd[3] v cc rx dd[6] tx ctd[0] tx dd[4] tx dd[3] w rx da[1] rx da[4] ref clka+ lfia v cc tx da[6] tx da[2] gnd tx erra rx clka+ addr [1] addr [3] gnd rx std[1] rx dd[4] v cc rx clkd C lfid tx dd[7] tx dd[5] y rx da[5] rx da[6] ref clka C tx errd v cc tx da[5] tx da[0] gnd rx clka C tx clka nc tx clkod gnd rx dd[0] rx dd[5] v cc rx clkd+ rx dd[7] tx clkd tx dd[6]
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 7 of 43 pin definitions cyp(v)15g0403dxb quad hotlink ii transceiver name i/o characteristicssignal description transmit path data and status signals txda[7:0] txdb[7:0] txdc[7:0] txdd[7:0] lvttl input, synchronous, sampled by the associated txclkx or refclkx [2] transmit data inputs . txdx[7:0] data inputs are captured on the rising edge of the transmit interface clock. the transmit interface clock is selected by the txckselx latch via the device configuration interface, and passed to the encoder or transmit shifter. when the encoder is enabled, txdx[7:0] specifies the specific data or command character sent. txcta[1:0] txctb[1:0] txctc[1:0] txctd[1:0] lvttl input, synchronous, sampled by the associated txclkx or refclkx [2] transmit control . txctx[1:0] inputs are captured on the rising edge of the transmit interface clock. the transmit interface clock is selected by the txckselx latch via the device configuration interface, and passed to the encoder or transmit shifter. the txcta[1:0] inputs identify how the associated txdx[7:0] characters are interpreted. when the encoder is bypassed, these inputs are interpreted as data bits. when the encoder is enabled, these inputs determine if the txdx[7:0] character is encoded as data, a special character code, or replaced with other special character codes. see table3 for details. txerra txerrb txerrc txerrd lvttl output, synchronous to refclkx [3] , synchronous to rxclkx when selected as refclkx, asynchronous to transmit channel enable / disable, asynchronous to loss or return of refclkx transmit path error . txerrx is asserted high to indicate detection of a transmit phase-align buffer underflow or overflow. if an underflow or overflow condition is detected, txerrx, for the channel in error, is asserted high and remains asserted until either a word sync sequence is transmitted on that channel, or the transmit phase-align buffer is re-centered with the pabrstx latch via the device configuration interface. when txbistx = 0, the bist progress is presented on the associated txerrx output. the txerrx signal pulses high for one transmit- character clock period to indicate a pass through the bist sequence once every 511 or 527 (depending on rxckselx) character times. if rxckselx = 1, a one character pulse occurs every 527 character times. if rxckselx = 0, a one character pulse occurs every 511 character times. txerrx is also asserted high, when any of the following conditions is true: ? the txpll for the associated channel is powered down. this occurs when oe2x and oe1x for a given channel are both disabled by setting oe2x = 0 and oe1x = 0. ? the absence of the refclkx signal transmit path clock signals refclka refclkb refclkc refclkd differential lvpecl or single-ended lvttl input clock reference clock . refclkx clock inputs are used as the timing references for the transmit and receive plls. these input clocks may also be selected to clock the transmit and receive parallel interfaces. when driven by a single-ended lvcmos or lvttl clock source, connect the clock source to either the true or complement refclkx input, and leave the alternate refclkx input open (floating). when driven by an lvpecl clock source, the clock must be a differential clock, using both inputs. txclka txclkb txclkc txclkd lvttl clock input, internal pull-down transmit path input clock . when configuration latch txckselx = 0, the associated txclkx input is selected as the character-rate input clock for the txdx[7:0] and txctx[1:0] inputs. in this mode, the txclkx input must be frequency-coherent to its associated txclkox output clock, but may be offset in phase by any amount. once initialized, txclkx is allowed to drift in phase as much as 180 degrees. if the input phase of txclkx drifts beyond the handling capacity of the phase align buffer, txerrx is asserted to indicate the loss of data, and remains asserted until the phase align buffer is initialized. the phase of the txclkx input clock relative to its associated refclkx is initialized when the configuration latch pabrstx is written as 0. when the associated txerrx is deasserted, the phase align buffer is initialized and input characters are correctly captured. notes: 2.when refclkx is configured for half-rate operation, these inputs are sampled relative to both the rising and falling edges of the associated refclkx . 3.when refclkx is configured for half-rate operation, these outputs are presented relative to both the rising and falling edges of the associated refclkx .
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 8 of 43 txclkoa txclkob txclkoc txclkod lvttl output transmit clock output . txclkox output clock is synthesized by each channel s transmit pll and operates synchronous to the internal transmit character clock. txclkox operates at either the same frequency as refclkx (txratex = 0), or at twice the frequency of refclkx (txratex = 1). the transmit clock outputs have no fixed phase relationship to refclkx . receive path data and status signals rxda[7:0] rxdb[7:0] rxdc[7:0] rxdd[7:0] lvttl output, synchronous to the selected rxclk output or refclkx input parallel data output . rxdx[7:0] parallel data outputs change relative to the receive interface clock. the receive interface clock is selected by the rxckselx latch. if rxclkx is a full-rate clock, the rxclkx clock outputs are comple- mentary clocks operating at the character rate. the rxdx[7:0] outputs for the associated receive channels follow rising edge of rxclkx+ or falling edge of rxclkx C . if rxclkx is a half-rate clock, the rxclkx clock outputs are complementary clocks operating at half the character rate. the rxdx[7:0] outputs for the associated receive channels follow both the falling and rising edges of the associated rxclkx clock outputs. rxsta[2:0] rxstb[2:0] rxstc[2:0] rxstd[2:0] lvttl output, synchronous to the selected rxclk output or refclkx input parallel status output . rxsta[2:0] status outputs change relative to the receive interface clock. the receive interface clock is selected by the rxckselx latch. if rxclkx is a full-rate clock, the rxclkx clock outputs are complementary clocks operating at the character rate. the rxstax[2:0] outputs for the associated receive channels follow rising edge of rxclkx+ or falling edge of rxclkx C . if rxclkx is a half-rate clock, the rxclkx clock outputs are complementary clocks operating at half the character rate. the rxstax[2:0] outputs for the associated receive channels follow both the falling and rising edges of the associated rxclkx clock outputs. when the decoder is bypassed, rxstx[1:0] become the two low-order bits of the 10-bit received character. rxstx[2]=high indicates the presence of a comma character in the output register. when the decoder is enabled, rxstx[2:0] provide status of the received signal. see table11 for a list of received character status. receive path clock signals rxclka rxclkb rxclkc rxclkd lvttl output clock receive clock output . rxclkx is the receive interface clock used to control timing of the rxdx[7:0] and rxsta[2:0] parallel outputs. the source of the rxclkx outputs is selected by the rxckselx latch via the device configuration interface. these true and complement clocks are used to control timing of data output transfers. these clocks are output continuously at either the dual-character rate (1/20 th the serial bit-rate) or character rate (1/10 th the serial bit-rate) of the data being received, as selected by rxratex. when configured such that the output data path is clocked by the refclkx instead of a recovered clock, the rxclkx output drivers present a buffered or divided form (depending on rxratex) of the associated refclkx that are delayed in phase to align with the data. this phase difference allows the user to select the optimal clock (refclkx or rxclk ) for setup/hold timing for their specific system. when refclkx is a full-rate clock, the rxclkx rate depends on the value of rxratex. when refclkx is a half-rate clock and rxckselx = 0, the rxclkx rate depends on the value of rxratex. when refclkx is a half-rate clock and rxckselx=1, the rxclkx rate does not depend on the value of rxratex and operates at the same rate as refclkx . device control signals reset lvttl input, asynchronous, internal pull-up asynchronous device reset .reset initializes all state machines, counters, and configuration latches in the device to a known state. reset must be asserted low for a minimum pulse width. when the reset is removed, all state machines, counters and configuration latches are at an initial state. see table9 for the initialize values of the device configuration latches. pin definitions (continued) cyp(v)15g0403dxb quad hotlink ii transceiver namei/o characteristicssignal description
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 9 of 43 ldtden lvttl input, internal pull-up level detect transition density enable . when ldtden is high, the signal level detector, range controller, and transition density detector are all enabled to determine if the rxpll tracks refclkx or the selected input serial data stream. if the signal level detector, range controller, or transition density detector are out of their respective limits while ldtden is high, the rxpll locks to refclk until such a time they become valid. the (sdasel[a..d][1:0]) are used to configure the trip level of the signal level detector. the transition density detector limit is one transition in every 60 consecutive bits. when ldtden is low, only the range controller is used to determine if the rxpll tracks refclkx or the selected input serial data stream. for the cases when rxckselx = 0 (recovered clock), it is recommended to set ldtden = high. ulca ulcb ulcc ulcd lvttl input, internal pull-up use local clock . when ulcx is low, the rxpll is forced to lock to refclkx instead of the received serial data stream. while ulcx is low, the lfix for the associated channel is low indicating a link fault. when ulcx is high, the rxpll performs clock and data recovery functions on the input data streams. this function is used in applications in which a stable rxclkx is needed. in cases when there is an absence of valid data transitions for a long period of time, or the high-gain differential serial inputs (inx ) are left floating, there may be brief frequency excursions of the rxclkx outputs from refclkx . spdsela spdselb spdselc spdseld 3-level select [4] static control input serial rate select . the spdselx inputs specify the operating signaling-rate range of each channel s transmit and receive pll. low =195 C 400mbd mid = 400 C 800 mbd high = 800 C 1500mbd. insela inselb inselc inseld lvttl input, asynchronous receive input selector . the inselx input determines which external serial bit stream is passed to the receiver s clock and data recovery circuit. when inselx is high, the primary differential serial data input, inx1 , is selected for the associated receive channel. when inselx is low, the secondary differential serial data input, inx2 , is selected for the associated receive channel. lpena lpenb lpenc lpend lvttl input, asynchronous, internal pull-down loop-back-enable . the lpenx input enables the internal serial loop-back for the associated channel. when lpenx is high, the transmit serial data from the associated channel is internally routed to the associated receive clock and data recovery (cdr) circuit. all enabled serial drivers on the channel are forced to differential logic-1, and the serial data inputs are ignored. when lpenx is low, the internal serial loop-back function is disabled. lfia lfib lfic lfid lvttl output, asynchronous link fault indication output .lfix is an output status indicator signal. lfix is the logical or of six internal conditions. lfix is asserted low when any of the following conditions is true: ? received serial data rate outside expected range ? analog amplitude below expected levels ? transition density lower than expected ? receive channel disabled ? ulcx is low ? absence of refclkx . device configuration and control bus signals wren lvttl input, asynchronous, internal pull-up control write enable . the wren input writes the values of the data[7:0] bus into the latch specified by the address location on the addr[3:0] bus. [5] notes: 4.3-level select inputs are used for static configuration. these are ternary inputs that make use of logic levels of low, mid, and high. the low level is usually implemented by direct connection to v ss (ground). the high level is usually implemented by direct connection to v cc (power). the mid level is usually implemented by not connecting the input (left floating), which allows it to self bias to the proper level. 5.see device configuration and control interface for detailed information on the operation of the configuration interface. pin definitions (continued) cyp(v)15g0403dxb quad hotlink ii transceiver namei/o characteristicssignal description
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 10 of 43 addr[3:0] lvttl input asynchronous, internal pull-up control addressing bus . the addr[3:0] bus is the input address bus used to configure the device. the wren input writes the values of the data[7:0] bus into the latch specified by the address location on the addr[3:0] bus. [5] table9 lists the configuration latches within the device, and the initialization value of the latches upon the assertion of reset . table10 shows how the latches are mapped in the device. data[7:0] lvttl input asynchronous, internal pull-up control data bus . the data[7:0] bus is the input data bus used to configure the device. the wren input writes the values of the data[7:0] bus into the latch specified by address location on the addr[3:0] bus. [5 ] table9 lists the configu- ration latches within the device, and the initialization value of the latches upon the assertion of reset . table10 shows how the latches are mapped in the device. internal device configuration latches rfmode[a..d][1:0]internal latch [6] reframe mode select . framchar[a..d]internal latch [6] framing character select . decmode[a..d]internal latch [6] receiver decoder mode select . decbyp[a..d] internal latch [6] receiver decoder bypass . rxcksel[a..d] internal latch [6] receive clock select . rxrate[a..d] internal latch [6] receive clock rate select . sdasel[a..d][1:0]internal latch [6] signal detect amplitude select . encbyp[a..d] internal latch [6] transmit encoder bypassed . txcksel[a..d] internal latch [6] transmit clock select . txrate[a..d] internal latch [6] transmit pll clock rate select . rfen[a..d] internal latch [6] reframe enable . rxpllpd[a..d] internal latch [6] receive channel power control . rxbist[a..d] internal latch [6] receive bist disabled . txbist[a..d] internal latch [6] transmit bist disabled . oe2[a..d] internal latch [6] differential serial output driver 2 enable . oe1[a..d] internal latch [6] differential serial output driver 1 enable . pabrst[a..d] internal latch [6] transmit clock phase alignment buffer reset . glen[11..0] internal latch [6] global latch enable . fglen[2..0] internal latch [6] force global latch enable . factory test modes lten1 lvttl input, internal pull-down factory test 1 . lten1 input is for factory testing only. this input may be left as a no connect, or gnd only. scanen2 lvttl input, internal pull-down factory test 2. scanen2 input is for factory testing only. this input may be left as a no connect, or gnd only. tmen3 lvttl input, internal pull-down factory test 3 . tmen3 input is for factory testing only. this input may be left as a no connect, or gnd only. note: 6.see device configuration and control interface for detailed information on the internal latches. pin definitions (continued) cyp(v)15g0403dxb quad hotlink ii transceiver namei/o characteristicssignal description
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 11 of 43 cyp(v)15g0403dxb hotlink ii operation the cyp(v)15g0403dxb is a highly configurable, independent clocking, quad-channel transceiver designed to support reliable transfer of large quantities of data, using high-speed serial links from multiple sources to multiple destinations. this device supports four single-byte channels. cyp(v)15g0403dxb transmit data path input register the bits in the input register for each channel support different assignments, based on if the input data is encoded or unencoded. these assignments are shown in table1 . when the encoder is enabled, each input register captures eight data bits and two control bits on each input clock cycle. when the encoder is bypassed, the control bits are part of the pre-encoded 10-bit character. when the encoder is enabled, the txctx[1:0] bits are inter- preted along with the associated txdx[7:0] character to generate a specific 10-bit transmission character. phase-align buffer data from each input register is passed to the associated phase-align buffer, when the txdx[7:0] and txctx[1:0] input registers are clocked using txclkx | (txckselx = 0 and txratex = 0). when the txdx[7:0] and txctx[1:0] input registers are clocked using refclkx (txckselx = 1) and refclkx is a full-rate clock, the associated phase alignment buffer in the transmit path is bypassed. these buffers are used to absorb clock phase differences between the txclkx input clock and the internal character clock for that channel. once initialized, txclkx is allowed to drift in phase as much as 180 degrees. if the input phase of txclkx drifts beyond the handling capacity of the phase align buffer, txerrx is analog i/o outa1 outb1 outc1 outd1 cml differential output primary differential serial data output . the outx1 pecl-compatible cml outputs (+3.3v referenced) are capable of driving terminated transmission lines or standard fiber-optic transmitter modules, and must be ac-coupled for pecl- compatible connections. outa2 outb2 outc2 outd2 cml differential output secondary differential serial data output . the outx2 pecl-compatible cml outputs (+3.3v referenced) are capable of driving terminated transmission lines or standard fiber-optic transmitter modules, and must be ac-coupled for pecl-compatible connections. ina1 inb1 inc1 ind1 differential input primary differential serial data input . the inx1 input accepts the serial data stream for deserialization and decoding. the inx1 serial stream is passed to the receive cdr circuit to extract the data content when inselx = high. ina2 inb2 inc2 ind2 differential input secondary differential serial data input . the inx2 input accepts the serial data stream for deserialization and decoding. the inx2 serial stream is passed to the receiver cdr circuit to extract the data content when inselx = low. jtag interface tms lvttl input, internal pull-up test mode select . used to control access to the jtag test modes. if maintained high for 5 tclk cycles, the jtag test controller is reset. tclk lvttl input, internal pull-down jtag test clock . tdo 3-state lvttl output test data out . jtag data output buffer. high-z while jtag test mode is not selected. tdi lvttl input, internal pull-up test data in . jtag data input port. trst lvttl input, internal pull-up jtag reset signal . when asserted (low), this input asynchronously resets the jtag test access port controller. power v cc +3.3v power . gnd signal and power ground for all internal circuits . pin definitions (continued) cyp(v)15g0403dxb quad hotlink ii transceiver namei/o characteristicssignal description
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 12 of 43 asserted to indicate the loss of data, and remains asserted until the phase align buffer is initialized. the phase of the txclkx relative to its associated internal character rate clock is initialized when the configuration latch pabrstx is written as 0. when the associated txerrx is deasserted, the phase align buffer is initialized and input characters are correctly captured. if the phase offset, between the initialized location of the input clock and refclkx | , exceeds the skew handling capabilities of the phase-align buffer, an error is reported on that channel s txerrx output. this output indicates an error continuously until the phase-align buffer for that channel is reset. while the error remains active, the transmitter for that channel outputs a continuous c0.7 character to indicate to the remote receiver that an error condition is present in the link. each phase-align buffer may be individually reset with minimal disruption of the serial data stream. when a phase- align buffer error is present, the transmission of a word sync sequence re-centers the phase-align buffer and clears the error indication. note . k28.5 characters may be added or removed from the data stream during the phase align buffer reset operation. when used with non-cypress devices that require a complete 16-character word sync sequence for proper receive elasticity buffer operation, it is recommend that the phase alignment buffer reset be followed by a word sync sequence to ensure proper operation. encoder each character received from the input register or phase- align buffer is passed to the encoder logic. this block inter- prets each character and any associated control bits, and outputs a 10-bit transmission character. depending on the operational mode, the generated trans- mission character may be ? the 10-bit pre-encoded character accepted in the input register. ? the 10-bit equivalent of the 8-bit data character accepted in the input register. ? the 10-bit equivalent of the 8-bit special character code accepted in the input register. ? the 10-bit equivalent of the c0.7 violation character if a phase-align buffer overflow or underflow error is present. ? a character that is part of the 511-character bist sequence. ? a k28.5 character generated as an individual character or as part of the 16-character word sync sequence. data encoding raw data, as received directly from the transmit input register, is seldom in a form suitable for transmission across a serial link. the characters must usually be processed or transformed to guarantee ? a minimum transition density (to allow the receive pll to extract a clock from the serial data stream). ? a dc-balance in the signaling (to prevent baseline wander). ? run-length limits in the serial data (to limit the bandwidth requirements of the serial link). ? the remote receiver a way of determining the correct character boundaries (framing). when the encoder is enabled (encbypx = 1), the characters transmitted are converted from data or special character codes to 10-bit transmission characters, using an integrated 8b/10b encoder. when directed to encode the character as a special character code, the encoder uses the special character encoding rules listed in table16 . when directed to encode the character as a data character, it is encoded using the data character encoding rules in table15 . the 8b/10b encoder is standards compliant with ansi/ncits asc x3.230-1994 fibre channel, ieee 802.3z gigabit ethernet, the ibm ? escon ? and ficon ? channels, etsi dvb-asi, and atm forum standards for data transport. many of the special character codes listed in table16 may be generated by more than one input character. the cyp(v)15g0403dxb is designed to support two independent (but non-overlapping) special character code tables. this allows the cyp(v)15g0403dxb to operate in mixed environ- ments with other cypress hotlink devices using the enhanced cypress command code set, and the reduced command sets of other non-cypress devices. even when used in an environment that normally uses non-cypress special character codes, the selective use of cypress command codes can permit operation where running disparity and error handling must be managed. following conversion of each input character from eight bits to a 10-bit transmission character, it is passed to the transmit shifter and is shifted out lsb first, as required by ansi and ieee standards for 8b/10b coded serial data streams. transmit modes encoder bypass when the encoder is bypassed, the character captured from the txdx[7:0] and txctx[1:0] input register is passed directly to the transmit shifter without modification. with the encoder bypassed, the txctx[1:0] inputs are considered part of the data character and do not perform a control function that would otherwise modify the interpretation of the txdx[7:0] bits. the bit usage and mapping of these control bits when the encoder is bypassed is shown in table2 . note: 7.lsb shifted out first. table 1.input register bit assignments [7] signal name unencoded encoded txdx[0] (lsb) dinx[0] txdx[0] txdx[1] dinx[1] txdx[1] txdx[2] dinx[2] txdx[2] txdx[3] dinx[3] txdx[3] txdx[4] dinx[4] txdx[4] txdx[5] dinx[5] txdx[5] txdx[6] dinx[6] txdx[6] txdx[7] dinx[7] txdx[7] txctx[0] dinx[8] txctx[0] txctx[1] (msb) dinx[9] txctx[1]
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 13 of 43 when the encoder is enabled, the txctx[1:0] data control bits control the interpretation of the txdx[7:0] bits and the characters generated by them. these bits are interpreted as listed in table3 . word sync sequence when txctx[1:0]=11, a 16-character sequence of k28.5 characters, known as a word sync sequence, is generated on the associated channel. this sequence of k28.5 characters may start with either a positive or negative disparity k28.5 (as determined by the current running disparity and the 8b/10b coding rules). the disparity of the second and third k28.5 characters in this sequence are reversed from what normal 8b/10b coding rules would generate. the remaining k28.5 characters in the sequence follow all 8b/10b coding rules. the disparity of the generated k28.5 characters in this sequence follow a pattern of either ++ CC + C + C + C + C + C + C or CC ++ C + C + C + C + C + C +. the generation of this sequence, once started, cannot be stopped until all 16 characters have been sent. the content of the associated input registers are ignored for the duration of this sequence. at the end of this sequence, if the txctx[1:0] = 11 condition is sampled again, the sequence restarts and remains uninterruptible for the following 15 character clocks. transmit bist each transmit channel contains an internal pattern generator that can be used to validate both the link and device operation. these generators are enabled by the associated txbistx latch via the device configuration interface. when enabled, a register in the associated transmit channel becomes a signature pattern generator by logically converting to a linear feedback shift register (lfsr). this lfsr generates a 511- character (or 526-character) sequence that includes all data and special character codes, including the explicit violation symbols. this provides a predictable yet pseudo-random sequence that can be matched to an identical lfsr in the attached receiver(s). a device reset (reset sampled low) presets the bist enable latches to disable bist on all channels. all data and data-control information present at the associated txdx[7:0] and txctx[1:0] inputs are ignored when bist is active on that channel. if the receive channels are configured for reference clock operation, each pass is preceded by a 16- character word sync sequence to allow elasticity buffer alignment and management of clock-frequency variations. transmit pll clock multiplier each transmit pll clock multiplier accepts a character-rate or half-character-rate external clock at the associated refclkx input, and that clock is multiplied by 10 or 20 (as selected by txratex) to generate a bit-rate clock for use by the transmit shifter. it also provides a character-rate clock used by the transmit paths, and outputs this character rate clock as txclkox. each clock multiplier pll can accept a refclkx input between 19.5mhz and 150mhz, however, this clock range is limited by the operating mode of the cyp(v)15g0403dxb clock multiplier (txratex) and by the level on the associated spdselx input. spdselx are 3-level select [4] inputs that select one of three operating ranges for the serial data outputs and inputs of the associated channel. the operating serial signaling-rate and allowable range of refclkx frequencies are listed in table4 . table 2.encoder bypass mode signal name bus weight 10b name txdx[0] (lsb) 2 0 a [7] txdx[1] 2 1 b txdx[2] 2 2 c txdx[3] 2 3 d txdx[4] 2 4 e txdx[5] 2 5 i txdx[6] 2 6 f txdx[7] 2 7 g txctx[0] 2 8 h txctx[1] (msb) 2 9 j table 3. transmit modes txctx[1] tx- ctx[0] characters generated 0 0 encoded data character 0 1 k28.5 fill character 1 0 special character code 1 1 16-character word sync sequence table 4.operating speed settings spdselx txrate refclkx frequency (mhz) signaling rate (mbaud) low 1 reserved 195 C 400 0 19.5 C 40 mid (open) 1 20 C 40 400 C 800 0 40 C 80 high 1 40 C 75 800 C 1500 0 80 C 150
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 14 of 43 the refclkx inputs are differential inputs with each input internally biased to 1.4v. if the refclkx+ input is connected to a ttl, lvttl, or lvcmos clock source, the input signal is recognized when it passes through the internally biased reference point. when driven by a single-ended ttl, lvttl, or lvcmos clock source, connect the clock source to either the true or complement refclkx input, and leave the alternate refclkx input open (floating). when both the refclkx+ and refclkx C inputs are connected, the clock source must be a differential clock. this can either be a differential lvpecl clock that is dc-or ac-coupled or a differential lvttl or lvcmos clock. by connecting the refclkx C input to an external voltage source, it is possible to adjust the reference point of the refclkx+ input for alternate logic levels. when doing so it is necessary to ensure that the input differential crossing point remains within the parametric range supported by the input. serial output drivers the serial output interface drivers use differential current mode logic (cml) drivers to provide source-matched drivers for transmission lines. these drivers accept data from the transmit shifters. these drivers have signal swings equivalent to that of standard pecl drivers, and are capable of driving ac-coupled optical modules or transmission lines. when configured for local loopback (lpenx = high), all enabled serial drivers are configured to drive a static differential logic 1. transmit channels enabled each driver can be enabled or disabled separately via the device configuration interface. when a driver is disabled via the configuration interface, it is internally powered down to reduce device power. if both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. a device reset (reset sampled low) disables all output drivers. note . when a disabled transmit channel (i.e., both outputs disabled) is re-enabled: ? data on the serial outputs may not meet all timing specifi- cations for up to 250 s ? the state of the phase-align buffer cannot be guaranteed, and a phase-align reset is required if the phase-align buffer is used cyp(v)15g0403dxb receive data path serial line receivers two differential line receivers, inx1 and inx2 , are available on each channel for accepting serial data streams. the active serial line receiver on a channel is selected using the associated inselx input. the serial line receiver inputs are differential, and can accommodate wire interconnect and filtering losses or transmission line attenuation greater than 16db. for normal operation, these inputs should receive a signal of at least vi diff >100mv, or 200mv peak-to-peak differential. each line receiver can be dc- or ac-coupled to +3.3v powered fiber-optic interface modules (any ecl/pecl family, not limited to 100k pecl) or ac-coupled to +5v powered optical modules. the common-mode tolerance of these line receivers accommodates a wide range of signal termination voltages. each receiver provides internal dc- restoration, to the center of the receiver s common mode range, for ac-coupled signals. the local internal loopback (lpenx) allows the serial transmit data outputs to be routed internally back to the clock and data recovery circuit associated with each channel. when configured for local loopback, the associated transmit serial driver outputs are forced to output a differential logic-1. this prevents local diagnostic patterns from being broadcast to attached remote receivers. signal detect/link fault each selected line receiver (i.e., that routed to the clock and data recovery pll) is simultaneously monitored for ? analog amplitude above amplitude level selected by sdaselx ? transition density above the specified limit ? range controls report the received data stream inside normal frequency range ( 1500ppm [28] ) ? receive channel enabled ? presence of reference clock ? ulcx is not asserted. all of these conditions must be valid for the signal detect block to indicate a valid signal is present. this status is presented on thelfix (link fault indicator) output associated with each receive channel, which changes synchronous to the selected receive interface clock. analog amplitude while most signal monitors are based on fixed constants, the analog amplitude level detection is adjustable to allow operation with highly attenuated signals, or in high-noise environments. the analog amplitude level detection is set by the sdaselx latch via device configuration interface. the sdaselx latch sets the trip point for the detection of a valid signal at one of three levels, as listed in table5 . this control input affects the analog monitors for all receive channels. the analog signal detect monitors are active for the line receiver as selected by the associated inselx input. when configured for local loopback, no input receivers are selected, and the lfix output for each channel reports only the receive vco frequency out-of-range and transition density status of the associated transmit signal. when local loopback is active, the associated analog signal detect monitor is disabled. note: 8.the peak amplitudes listed in this table are for typical waveforms that have generally 3 C 4 transitions for every ten bits. in a worse case environment the signals may have a sine-wave appearance (highest transition density with repeating 0101...). signal peak amplitudes levels within this environment type could increase the values in the table above by approximately 100 mv. table 5.analog amplitude detect valid signal levels [8] sda- sel typical signal with peak amplitudes above 00 analog signal detector is disabled 01 140 mv p-p differential 10 280 mv p-p differential 11 420 mv p-p differential
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 15 of 43 transition density the transition detection logic checks for the absence of transitions spanning greater than six transmission characters (60 bits). if no transitions are present in the data received, the detection logic for that channel asserts lfix . range controls the cdr circuit includes logic to monitor the frequency of the pll voltage controlled oscillator (vco) used to sample the incoming data stream. this logic ensures that the vco operates at, or near the rate of the incoming data stream for two primary cases: ? when the incoming data stream resumes after a time in which it has been missing. ? when the incoming data stream is outside the acceptable signaling rate range. to perform this function, the frequency of the rxpll vco is periodically compared to the frequency of the refclkx input. if the vco is running at a frequency beyond 1500ppm [28] as defined by the refclkx frequency, it is periodically forced to the correct frequency (as defined by refclkx , spdselx, and txratex) and then released in an attempt to lock to the input data stream. the sampling and relock period of the range control is calcu- lated as follows: range_control_ sampling_period = (recovered byte clock period) * (4096). during the time that the range control forces the rxpll vco to track refclkx , the lfix output is asserted low. after a valid serial data stream is applied, it may take up to one range control sampling period before the pll locks to the input data stream, after which lfix should be high. receive channel enabled the cyp(v)15g0403dxb contains four receive channels that can be independently enabled and disabled. each channel can be enabled or disabled separately through the rxpllpdx input latch as controlled by the device configuration interface. when the rxpllpdx latch = 0, the associated pll and analog circuitry of the channel is disabled. any disabled channel indicates a constant link fault condition on the lfix output. when rxpllpdx = 1, the associated pll and receive channel is enabled to receive and decode a serial stream. note . when a disabled receive channel is reenabled, the status of the associated lfix output and data on the parallel outputs for the associated channel may be indeterminate for up to 2 ms. clock/data recovery the extraction of a bit-rate clock and recovery of bits from each received serial stream is performed by a separate cdr block within each receive channel. the clock extraction function is performed by an integrated pll that tracks the frequency of the transitions in the incoming bit stream and align the phase of the internal bit-rate clock to the transitions in the selected serial data stream. each cdr accepts a character-rate (bit-rate 10) or half- character-rate (bit-rate 20) reference clock from the associated refclkx input. this refclkx input is used to ? ensure that the vco (within the cdr) is operating at the correct frequency (rather than a harmonic of the bit-rate) ? reduce pll acquisition time ? limit unlocked frequency excursions of the cdr vco when there is no input data present at the selected serial line receiver. regardless of the type of signal present, the cdr attempts to recover a data stream from it. if the signalling rate of the recovered data stream is outside the limits set by the range control monitors, the cdr tracks refclkx instead of the data stream. once the cdr output (rxclk ) frequency returns back close to refclkx frequency, the cdr input is switched back to the input data stream. if no data is present at the selected line receiver, this switching behavior may result in brief rxclk frequency excursions from refclkx . however, the validity of the input data stream is indicated by thelfix output. the frequency of refclkx is required to be within 1500ppm [28] of the frequency of the clock that drives the refclkx input of the remote transmitter to ensure a lock to the incoming data stream. for systems using multiple or redundant connections, the lfix output can be used to select an alternate data stream. when an lfix indication is detected, external logic can toggle selection of the associated inx1 and inx2 input through the associated inselx input. when a port switch takes place, it is necessary for the receive pll for that channel to reacquire the new serial stream and frame to the incoming character bound- aries. deserializer/framer each cdr circuit extracts bits from the associated serial data stream and clocks these bits into the shifter/framer at the bit- clock rate. when enabled, the framer examines the data stream looking for one or more comma or k28.5 characters at all possible bit positions. the location of this character in the data stream is used to determine the character boundaries of all following characters. framing character the cyp(v)15g0403dxb allows selection of different framing characters on each channel. two combinations of framing characters are supported to meet the requirements of different interfaces. the selection of the framing character is made through the framcharx latches via the configuration interface. the specific bit combinations of these framing characters are listed in table6 . when the specific bit combination of the selected framing character is detected by the framer, the boundaries of the characters present in the received data stream are known. note: 9.the standard definition of a comma contains only seven bits. however, since all valid comma characters within the 8b/10b character set also have the eighth bit as an inversion of the seventh bit, the compare pattern is extended to a full eight bits to reduce the possibility of a framing error.
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 16 of 43 framer the framer on each channel operates in one of three different modes. each framer may be enabled or disabled using the rfenx latches via the configuration interface. when the framer is disabled (rfenx = 0), no combination of received bits alters the frame information. when the low-latency framer is selected (rfmodex[1:0] = 00), the framer operates by stretching the recovered character clock until it aligns with the received character boundaries. in this mode the framer starts its alignment process on the first detection of the selected framing character. to reduce the impact on external circuits that use the recovered clock, the clock period is not stretched by more than two bit-periods in any one clock cycle. when operated with a character-rate output clock, the output of properly framed characters may be delayed by up to nine character-clock cycles from the detection of the selected framing character. when operated with a half-character-rate output clock, the output of properly framed characters may be delayed by up to 14 character-clock cycles from the detection of the framing character. note .when receive bist is enabled on a channel, the low- latency framer must not be enabled. the bist sequence contains an aliased k28.5 framing character, which causes the receiver to update its character boundaries incorrectly. when rfmodex[1:0] = 10, the cypress-mode multi-byte framer is selected. the required detection of multiple framing characters makes the associated link much more robust to incorrect framing due to aliased sync characters in the data stream. in this mode, the framer does not adjust the character clock boundary, but instead aligns the character to the already recovered character clock. this ensures that the recovered clock does not contain any significant phase changes or hops during normal operation or framing, and allows the recovered clock to be replicated and distributed to other external circuits or components using pll-based clock distribution elements. in this framing mode the character boundaries are only adjusted if the selected framing character is detected at least twice within a span of 50 bits, with both instances on identical 10-bit character boundaries. when rfmodex[1:0] = 01, the alternate-mode multi-byte framer is enabled. like the cypress-mode multi-byte framer, multiple framing characters must be detected before the character boundary is adjusted. in this mode, the data stream must contain a minimum of four of the selected framing characters, received as consecutive characters, on identical 10-bit boundaries, before character framing is adjusted. 10b/8b decoder block the decoder logic block performs two primary functions: ? decoding the received transmission characters to data and special character codes ? comparing generated bist patterns with received characters to permit at-speed link and device testing. the framed parallel output of each deserializer shifter is passed to its associated 10b/8b decoder where, if the decoder is enabled, the input data is transformed from a 10-bit transmission character back to the original data or special character code. this block uses the 10b/8b decoder patterns in table15 and table16. received special code characters are decoded using table16 . valid data characters are indicated by a 000b bit-combination on the associated rxstx[2:0] status bits, and special character codes are indicated by a 001b bit-combination of these status outputs. framing characters, invalid patterns, disparity errors, and synchronization status are presented as alternate combina- tions of these status bits. when decbypx = 0, the 10b/8b decoder is bypassed via the configuration interface. when bypassed, raw 10-bit characters are passed through the receiver and presented at the rxdx[7:0] and the rxsta[1:0] outputs as 10-bit wide characters. when the decoder is enabled by setting decbypx = 1 via the configuration interface, the 10-bit transmission characters are decoded using table15 and table16 . received special characters are decoded using table16 . the columns used in table16 are determined by the decmodex latch via the device configuration interface. when decmodex = 0 the alternate table is used and when decmodex = 1 the cypress table is used. receive bist operation the receiver channel contains an internal pattern checker that can be used to validate both device and link operation. these pattern checkers are enabled by the associated rxbistx latch via the device configuration interface. when enabled, a register in the associated receive channel becomes a signature pattern generator and checker by logically converting to a linear feedback shift register (lfsr). this lfsr generates a 511-character or 526-character sequence that includes all data and special character codes, including the explicit violation symbols. this provides a predictable yet pseudo-random sequence that can be matched to an identical lfsr in the attached transmitter(s). when synchronized with the received data stream, the associated receiver checks each character in the decoder with each character generated by the lfsr and indicates compare errors and bist status at the rxstx[2:0] bits of the output register. when bist is first recognized as being enabled in the receiver, the lfsr is preset to the bist-loop start-code of d0.0. this code d0.0 is sent only once per bist loop. the status of the bist progress and any character mismatches are presented on the rxstx[2:0] status outputs. code rule violations or running disparity errors that occur as part of the bist loop do not cause an error indication. rxstx[2:0] indicates 010b or 100b for one character period per bist loop to indicate loop completion. this status can be used to check test pattern progress. these same status values are presented when the decoder is bypassed and bist is enabled on a receive channel. the specific status reported by the bist state machine are listed in table11 . these same codes are reported on the receive status outputs. table 6.framing character selector framcharx bits detected in framer character name bits detected 0 comma+ comma C 00111110xx [9] or 11000001xx 1 -k28.5 +k28.5 0011111010 or 1100000101
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 17 of 43 the specific patterns checked by each receiver are described in detail in the cypress application note hotlink built-in self- test. the sequence compared by the cyp(v)15g0403dxb is identical to that in the cy7b933, cy7c924dx, and cyp(v)15g0401dxb, allowing interoperable systems to be built when used at compatible serial signaling rates. if the number of invalid characters received ever exceeds the number of valid characters by 16, the receive bist state machine aborts the compare operations and resets the lfsr to the d0.0 state to look for the start of the bist sequence again. when the receive paths are configured for refclkx operation, each pass must be preceded by a 16-character word sync sequence to allow management of clock frequency variations. the receive bist state machine requires the characters to be correctly framed for it to detect the bist sequence. if the low latency framer is enabled, the framer misaligns to an aliased sync character within the bist sequence. if the alternate multi-byte framer is enabled and the receiver outputs are clocked relative to a recovered clock, it is generally necessary to frame the receiver before bist is enabled. if the receive outputs are clocked relative to refclkx , the transmitter precedes every 511 character bist sequence with a 16 character-character word sync sequence. a device reset (reset sampled low) presets the bist enable latches to disable bist on all channels. receive elasticity buffer each receive channel contains an elasticity buffer that is designed to support multiple clocking modes. these buffers allow data to be read using a clock that is asynchronous in both frequency and phase from the elasticity buffer write clock, or to be read using a clock that is frequency coherent but with uncontrolled phase relative to the elasticity buffer write clock. if the chip is configured for operation with a recovered clock, the elasticity buffer is bypassed. each elasticity buffer is 10 characters deep, and supports and an 11 bit wide data path. it is capable of supporting a decoded character and three status bits for each character present in the buffer. the write clock for these buffers is always the recovered clock for the associated read channel. receive modes when the receive channel is clocked by refclkx , the rxclkx outputs present a buffered or divided (depending on rxratex) and delayed form of refclkx . in this mode, the receive elasticity buffers are enabled. for refclkx clocking, the elasticity buffers must be able to insert k28.5 characters and delete framing characters as appropriate. the insertion of a k28.5 or deletion of a framing character can occur at any time on any channel, however, the actual timing of these insertions and deletions is controlled in part by how the transmitter sends its data. insertion of a k28.5 character can only occur when the receiver has a framing character in the elasticity buffer. likewise, to delete a framing character, one must also be in the elasticity buffer. to prevent a buffer overflow or underflow on a receive channel, a minimum density of framing characters must be present in the received data streams. when the receive channel output register is clocked by a recovered clock, no characters are added or deleted and the receiver elasticity buffer is bypassed. power control the cyp(v)15g0403dxb supports user control of the powered up or down state of each transmit and receive channel. the receive channels are controlled by the rxpllpdx latch via the device configuration interface. when rxpllpdx = 0, the associated pll and analog circuitry of the channel is disabled. the transmit channels are controlled by the oe1x and the oe2x latches via the device configuration interface. when a driver is disabled via the configuration interface, it is internally powered down to reduce device power. if both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. device reset state when the cyp(v)15g0403dxb is reset by assertion of reset , all state machines, counters, and configuration latches in the device are initialized to a reset state, and the elasticity buffer pointers are set to a nominal offset. see table9 for the initialize values of the configuration latches. following a device reset, it is necessary to enable the transmit and receive channels used for normal operation. this can be done by sequencing the appropriate values on the device configuration interface. [5] output bus each receive channel presents an 11-signal output bus consisting of ? an 8-bit data bus ? a 3-bit status bus. the signals present on this output bus are modified by the present operating mode of the cyp(v)15g0403dxb as selected by the decbypx configuration latch. this mapping is shown in table7 . table 7.output register bit assignments signal name bypass active (decbypx = 0) decoder (decbypx = 1) rxstx[2] (lsb) comdetx rxstx[2] rxstx[1] doutx[0] rxstx[1] rxstx[0] doutx[1] rxstx[0] rxdx[0] doutx[2] rxdx[0] rxdx[1] doutx[3] rxdx[1] rxdx[2] doutx[4] rxdx[2] rxdx[3] doutx[5] rxdx[3] rxdx[4] doutx[6] rxdx[4] rxdx[5] doutx[7] rxdx[5] rxdx[6] doutx[8] rxdx[6] rxdx[7] (msb) doutx[9] rxdx[7]
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 18 of 43 when the 10b/8b decoder is bypassed, the framed 10-bit value is presented to the associated output register, along with a status output signal indicating if the character in the output register is one of the selected framing characters. the bit usage and mapping of the external signals to the raw 10b transmission character is shown in table8 . the comdetx status output operates the same regardless of the bit combination selected for character framing by the framcharx latch. comdetx is high when the character in the output register contains the selected framing character at the proper character boundary, and low for all other bit combinations. when the low-latency framer and half-rate receive port clocking are also enabled, the framer stretches the recovered clock to the nearest 20-bit boundary such that the rising edge of rxclkx+ occurs when comdetx is present on the associated output bus. when the cypress or alternate mode framer is enabled and half-rate receive port clocking is also enabled, the output clock is not modified when framing is detected, but a single pipeline stage may be added or subtracted from the data stream by the framer logic such that the rising edge of rxclkx+ occurs when comdetx is present on the associated output bus. this adjustment only occurs when the framer is enabled. when the framer is disabled, the clock boundaries are not adjusted, and comdetx may be asserted during the rising edge of rxclkx C (if an odd number of characters were received following the initial framing). receive status bits when the 10b/8b decoder is enabled, each character presented at the output register includes three associated status bits. these bits are used to identify ? if the contents of the data bus are valid, ? the type of character present, ? the state of receive bist operations, ? character violations. these conditions often overlap; e.g. a valid data character received with incorrect running disparity is not reported as a valid data character. it is instead reported as a decoder violation of some specific type. this implies a hierarchy or priority level to the various status bit combinations. the hierarchy and value of each status are listed in table11 . a second status mapping, listed in table11 , is used when the receive channel is configured for bist operation. this status is used to report receive bist status and progress. bist status state machine when a receive path is enabled to look for and compare the received data stream with the bist pattern, the rxstx[2:0] bits identify the present state of the bist compare operation. the bist state machine has multiple states, as shown in figure2 and table11 . when the receive pll detects an out- of-lock condition, the bist state is forced to the start-of-bist state, regardless of the present state of the bist state machine. if the number of detected errors ever exceeds the number of valid matches by greater than 16, the state machine is forced to the wait_for_bist state where it monitors the receive path for the first character of the next bist sequence (d0.0). also, if the elasticity buffer ever hits an overflow/underflow condition, the status is forced to the bist_start until the buffer is re-centered (approximately nine character periods). to ensure compatibility between the source and destination systems when operating in bist modes, the sending and receiving ends of the link must use the same receive clock configuration. device configuration and control interface the cyp(v)15g0403dx is highly configurable via the config- uration interface. the configuration interface allows the device to be configured globally or allows each channel to be configured independently. table9 lists the configuration latches within the device including the initialization value of the latches upon the assertion of reset . table10 shows how the latches are mapped in the device. each row in the table10 maps to a 8-bit latch bank. there are 16 such write-only latch banks. when wren = 0, the logic value in the data[7:0] is latched to the latch bank specified by the values in addr[3:0]. the second column of table10 specifies the channels associated with the corresponding latch bank. for example, the first three latch banks (0,1 and 2) consist of configuration bits for channel a. the latch banks 12, 13 and 14 consist of global configuration bits and the last latch bank (15) is the mask latch bank that can be configured to perform bit-by-bit configuration. global enable function the global enable function, controlled by the glenx bits, is a feature that can be used to reduce the number of write opera- tions needed to setup the latch banks. this function is beneficial in systems that use a common configuration in multiple channels. the glenx bit is present in bit 0 of latch banks 0 through 11 only. its default value (1) enables the global update of the latch bank's contents. setting the glenx bit to 0 disables this functionality. latch banks 12, 13, and 14 are used to load values in the related latch banks in a global manner. a write operation to latch bank 12 could do a global write to latch banks 0, 3, 6, and 9 depending on the value of glenx in these latch banks; latch bank 13 could do a global write to latch banks 1, 4, 7 and 10; and latch banks 14 could do a global write to latch banks 2, 5, table 8.decoder bypass mode signal name bus weight 10 bit name rxstx[2] (lsb) comdetx rxstx[1] 2 0 a rxstx[0] 2 1 b rxdx[0] 2 2 c rxdx[1] 2 3 d rxdx[2] 2 4 e rxdx[3] 2 5 i rxdx[4] 2 6 f rxdx[5] 2 7 g rxdx[6] 2 8 h rxdx[7] (msb) 2 9 j
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 19 of 43 8 and 11. the glenx bit cannot be modified by a global write operation. force global enable function fglenx forces the global update of the target latch banks, but does not change the contents of the glenx bits. if fglenx = 1 for the associated global channel, fglenx forces the global update of the target latch banks. mask function an additional latch bank (15) is used as a global mask vector to control the update of the configuration latch banks on a bit- by-bit basis. a logic 1 in a bit location allows for the update of that same location of the target latch bank(s), whereas a logic 0 disables it. the reset value of this latch bank is ffh, thereby making its use optional by default. the mask latch bank is not maskable. the fglen functionality is not affected by the bit 0 value of the mask latch bank. latch types there are two types of latch banks: static (s) and dynamic (d). each channel is configured by 2 static and 1 dynamic latch banks. the s type contain those settings that normally do not change for a given application, whereas the d type controls the settings that could change dynamically during the appli- cation's lifetime.the first row of latches for each channel (address numbers 0, 3, 7, and 10) are the static receiver control latches. the second row of latches for each channel (address numbers 1, 4, 8, and 11) are the static transmitter control latches. the third row of latches for each channel (address numbers 2, 5, 9, and 12) are the dynamic control latches that are associated with enabling dynamic functions within the device. latch bank 14 is also useful for those users that do not need the latch-based programmable feature of the device. this latch bank could be used in those applications that do not need to modify the default value of the static latch banks, and that can afford a global (i.e., not independent) control of the dynamic signals. in this case, this feature becomes available when addr[3:0] is left unchanged with a value of 1110 and wren is left asserted. the signals present in data[7:0] effec- tively become global control pins, and for the latch banks 2, 5, 8 and 11. table 9.device configuration and control latch descriptions name signal description rfmodea[1:0] rfmodeb[1:0] rfmodec[1:0] rfmoded[1:0] reframe mode select . the initialization value of the rfmodex [1:0] latches = 10. rfmodex is used to select the operating mode of the framer. when rfmodex[1:0]=00, the low-latency framer is selected. this frames on each occurrence of the selected framing character(s) in the received data stream. this mode of framing stretches the recovered clock for one or multiple cycles to align that clock with the recovered data. when rfmodex[1:0]=01, the alternate mode multi-byte parallel framer is selected. this requires detection of the selected framing character(s) in the received serial bit stream, on identical 10-bit boundaries, on four directly adjacent characters. the recovered character clock remains in the same phasing regardless of character offset. when rfmodex[1:0] =10, the cypress-mode multi-byte parallel framer is selected. this requires a pair of the selected framing character(s), on identical 10-bit boundaries, within a span of 50 bits, before the character boundaries are adjusted. the recovered character clock remains in the same phasing regardless of character offset. rfmodex[1:0] = 11 is reserved for test. framchara framcharb framcharc framchard framing character select . the initialization value of the framcharx latch = 1. framcharx is used to select the character or portion of a character used for framing of each channel s received data stream. when framcharx = 1, the framer looks for either disparity of the k28.5 character. when framcharx = 0, the framer looks for either disparity of the 8-bit comma characters. the specific bit combinations of these framing characters are listed in table6 . decmodea decmodeb decmodec decmoded receiver decoder mode select . the initialization value of the decmodex latch = 1. decmodex selects the decoder mode used for the associated channel. when decmodex = 1 and decoder is enabled, the cypress decoding mode is used. when decmodex = 0 and decoder is enabled, the alternate decoding mode is used. when the decoder is enabled (decbypx = 1), the 10-bit transmission characters are decoded using table15 and table16 . the column used in the special characters table16 is determined by the decmodex latch. decbypa decbypb decbypc decbypd receiver decoder bypass . the initialization value of the decbypx latch = 1. decbypx selects if the receiver decoder is enabled or bypassed. when decbypx = 1, the decoder is enabled and the decoder mode is selected by decmodex. when decbypx = 0, the decoder is bypassed and raw 10-bit characters are passed through the receiver. rxcksela rxckselb rxckselc rxckseld receive clock select . the initialization value of the rxckselx latch = 1.rxckselx selects the receive clock source used to transfer data to the output registers and the clock source for the rxclk output. when rxckselx = 1, the associated output registers are clocked by refclkx at the associated rxclkx output buffer. when rxckselx = 0, the associated output registers, are clocked by the recovered byte clock at the associated rxclkx output buffer. these output clocks may operate at the character-rate or half the character-rate as selected by rxratex.
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 20 of 43 rxratea rxrateb rxratec rxrated receive clock rate select . the initialization value of the rxratex latch = 1. rxratex is used to select the rate of the rxclkx clock output. when rxratex = 1 and rxckselx = 0, the rxclkx clock outputs are complementary clocks that follow the recovered clock operating at half the character rate. data for the associated receive channels should be latched alternately on the rising edge of rxclkx+ and rxclkx C . when rxratex = 0 and rxckselx = 0, the rxclkx clock outputs are complementary clocks that follow the recovered clock operating at the character rate. data for the associated receive channels should be latched on the rising edge of rxclkx+ or falling edge of rxclkx C . when rxratex = 1 with rxckselx = 1 and refclkx is a full-rate clock, the rxclkx clock outputs are complementary clocks that follow the reference clock operating at half the character rate. data for the associated receive channels should be latched alternately on the rising edge of rxclkx+ and rxclkx C . when rxratex = 0 with rxckselx = 1 and refclkx is a full-rate clock, the rxclkx clock outputs are complementary clocks that follow the reference clock operating at the character rate. data for the associated receive channels should be latched on the rising edge of rxclkx+ or falling edge of rxclkx C . when rxckselx = 1 and refclkx is a half-rate clock, the value of rxratex is not interpreted and the rxclkx clock outputs are complementary clocks that follow the reference clock operating at half the character rate. data for the associated receive channels should be latched alternately on the rising edge of rxclkx+ and rxclkx C . sdasel1a[1:0] sdasel1b[1:0] sdasel1c[1:0] sdasel1d[1:0] primary serial data input signal detector amplitude select . the initialization value of the sdasel1x[1:0] latch = 10. sdasel1x[1:0] selects the trip point for the detection of a valid signal for the inx1 primary differential serial data inputs. when sdasel1x[1:0] = 00, the analog signal detector is disabled. when sdasel1x[1:0] = 01, the typical p-p differential voltage threshold level is 140mv. when sdasel1x[1:0] = 10, the typical p-p differential voltage threshold level is 280mv. when sdasel1x[1:0] = 11, the typical p-p differential voltage threshold level is 420mv. sdasel2a[1:0] sdasel2b[1:0] sdasel2c[1:0] sdasel2d[1:0] secondary serial data input signal detector amplitude select . the initialization value of the sdasel2x[1:0] latch = 10. sdasel2x[1:0] selects the trip point for the detection of a valid signal for the inx2 secondary differential serial data inputs. when sdasel2x[1:0] = 00, the analog signal detector is disabled when sdasel2x[1:0] = 01, the typical p-p differential voltage threshold level is 140mv. when sdasel2x[1:0] = 10, the typical p-p differential voltage threshold level is 280mv. when sdasel2x[1:0] = 11, the typical p-p differential voltage threshold level is 420mv. encbypa encbypb encbypc encbypd transmit encoder bypassed . the initialization value of the encbypx latch = 1. encbypx selects if the transmit encoder is enabled or bypassed. when encbypx = 1, the transmit encoder is enabled. when encbypx = 0, the transmit encoder is bypassed and raw 10-bit characters are transmitted. txcksela txckselb txckselc txckseld transmit clock select . the initialization value of the txckselx latch = 1. txckselx selects the clock source used to write data into the transmit input register. when txckselx = 1, the associated input register, txdx[7:0] and txctx[1:0], is clocked by refclkx in this mode, the phase alignment buffer in the transmit path is bypassed. when txckselx = 0, the associated txclkx is used to clock in the input registers, txdx[7:0] and txctx[1:0]. txratea txrateb txratec txrated transmit pll clock rate select . the initialization value of the txratex latch = 0. txratex is used to select the clock multiplier for the transmit pll. when txratex= 0, each transmit pll multiples the associated refclkx input by 10 to generate the serial bit-rate clock. when txratex=0, the txclkox output clocks are full-rate clocks and follow the frequency and duty cycle of the associated refclkx input. when txratex= 1, each transmit pll multiplies the associated refclkx input by 20 to generate the serial bit-rate clock. when txratex = 1, the txclkox output clocks are twice the frequency rate of the refclkx input. when txckselx = 1 and txratex = 1, the transmit data inputs are captured using both the rising and falling edges of refclkx. txratex = 1 and spdselx is low, is an invalid state and this combination is reserved. rfena rfenb rfenc rfend reframe enable . the initialization value of the rfenx latch = 1. rfenx selects if the receiver framer is enabled or disabled. when rfenx = 1, the associated channel s framer is enabled to frame per the presently enabled framing mode and selected framing character. when rfenx = 0, the associated channel s framer is disabled, and no received bits alters the frame offset. table 9. device configuration and control latch descriptions (continued)
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 21 of 43 device configuration strategy the following is a series of ordered events needed to load the configuration latches on a per channel basis: 1.pulse reset low after device power-up. this operation resets all four channels. 2.set the static receiver latch bank for the target channel. may be performed using a global operation, if the application permits it. [optional step if the default settings match the desired configuration.] 3.set the static transmitter latch bank for the target channel. may be performed using a global operation, if the appli- cation permits it. [optional step if the default settings match the desired configuration.] 4.set the dynamic bank of latches for the target channel. enable the receive plls and transmit channels. may be performed using a global operation, if the application permits it. [required step.] 5.reset the phase alignment buffer for the target channel. may be performed using a global operation, if the appli- cation permits it. [optional if phase align buffer is bypassed.] when a receive channel is configured with the decoder bypassed and the receive clock selected as recovered clock in half-rate mode (decbypx = 0, rxratex = 1, rxckselx = 0), the channel cannot be dynamically reconfigured to enable the decoder with rxclkx selected as the refclkx (decbypx = 1, rxckselx = 1). if such a change is desired, a global reset should be performed and all channels should be reconfigured to the desired settings. rxpllpda rxpllpdb rxpllpdc rxpllpdd receive channel enable . the initialization value of the rxpllpdx latch = 0. rxpllpdx selects if the associated receive channel is enabled or powered-down. when rxpllpdx = 0, the associated pll and analog circuitry is powered-down. when rxpllpdx = 1, the associated pll and analog circuitry is enabled. rxbista rxbistb rxbistc rxbistd receive bist disabled . the initialization value of the rxbistx latch = 1. rxbistx selects if receive bist is disabled or enabled. when rxbistx = 1, the receiver bist function is disabled. when rxbistx = 0, the receive bist function is enabled. txbista txbistb txbistc txbistd transmit bist disabled . the initialization value of the txbistx latch = 1. txbistx selects if the transmit bist is disabled or enabled. when txbistx = 1, the transmit bist function is disabled. when txbistx=0, the transmit bist function is enabled. oe2a oe2b oe2c oe2d secondary differential serial data output driver enable . the initialization value of the oe2x latch = 0. oe2x selects if the out2 secondary differential output drivers are enabled or disabled. when oe2x = 1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter. when oe2x = 0, the associated serial data output driver is disabled. when a driver is disabled via the configuration interface, it is internally powered down to reduce device power. if both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. adevice reset (reset sampled low) disables all output drivers. oe1a oe1b oe1c oe1d primary differential serial data output driver enable . the initialization value of the oe1x latch = 0. oe1x selects if the out1 primary differential output drivers are enabled or disabled. when oe1x = 1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter. when oe1x = 0, the associated serial data output driver is disabled. when a driver is disabled via the configuration interface, it is internally powered down to reduce device power. if both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. adevice reset (reset sampled low) disables all output drivers. pabrsta pabrstb pabrstc pabrstd transmit clock phase alignment buffer reset . the initialization value of the pabrstx latch = 1. the pabrstx is used to re-center the transmit phase align buffer. when the configuration latch pabrstx is written as a 0, the phase of the txclkx input clock relative to its associated refclkx+/- is initialized. pabrst is an asynchronous input, but is sampled by each txclkx to synchronize it to the internal clock domain. pabrstx is a self clearing latch. this eliminates the requirement of writing a 1 to complete the initialization of the phase alignment buffer. glen[11..0] global enable . the initialization value of the glenx latch = 1. the glenx is used to reconfigure several channels simultaneously in applications where several channels may have the same configuration. when glenx = 1 for a given address, that address is allowed to participate in a global configuration. when glenx = 0 for a given address, that address is disabled from participating in a global configuration. fglen[2..0] force global enable . the initialization value of the fglenx latch is na. the fglenx latch forces a global enable no matter what the setting is on the glenx latch. if fglenx = 1 for the associated global channel, fglen forces the global update of the target latch banks. table 9. device configuration and control latch descriptions (continued)
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 22 of 43 jtag support the cyp(v)15g0403dxb contains a jtag port to allow system level diagnosis of device interconnect. of the available jtag modes, boundary scan, and bypass are supported. this capability is present only on the lvttl inputs and outputs and the refclkx clock input. the high-speed serial inputs and outputs are not part of the jtag test chain. 3-level select inputs each 3-level select inputs reports as two bits in the scan register. these bits report the low, mid, and high state of the associated input as 00, 10, and 11 respectively jtag id the jtag device id for the cyp(v)15g0403dxb is 0c810069 x. table 10.device control latch configuration table addrchanneltype data7 data6 data5 data4 data3 data2 data1data0 reset value 0 (0000b) a srfmodea[1]rfmodea[0]framcharadecmodeadecbyparxckselarxrateaglen010111111 1 (0001b) a ssdasel2a[1]sdasel2a[0]sdasel1a[1]sdasel1a[0]encbypatxckselatxrateaglen110101101 2 (0010b) a d rfena rxpllpda rxbista txbista oe2a oe1a pabrstaglen210110011 3 (0011b) b srfmodeb[1]rfmodeb[0]framcharbdecmodebdecbypbrxckselbrxratebglen310111111 4 (0100b) b ssdasel2b[1]sdasel2b[0]sdasel1b[1]sdasel1b[0]encbypbtxckselbtxratebglen410101101 5 (0101b) b d rfenb rxpllpdb rxbistb txbistb oe2b oe1b pabrstbglen510110011 6 (0110b) c srfmodec[1]rfmodec[0]framcharcdecmodecdecbypcrxckselcrxratecglen610111111 7 (0111b) c ssdasel2c[1]sdasel2c[0]sdasel1c[1]sdasel1c[0]encbypctxckselctxratecglen710101101 8 (1000b) c d rfenc rxpllpdc rxbistc txbistc oe2c oe1c pabrstcglen810110011 9 (1001b) d srfmoded[1]rfmoded[0]framcharddecmodeddecbypdrxckseldrxrate dglen910111111 10 (1010b) d ssdasel2d[1]sdasel2d[0]sdasel1d[1]sdasel1d[0]encbypdtxckseldtxratedglen1010101101 11 (1011b) d d rfend rxpllpdd rxbistd txbistd oe2d oe1d pabrstdglen1110110011 12 (1100b) globalsrfmodegl[1]rfmode gl[0] framchargldecmodegldecbypglrxckselglrxrateg l fglen0 n/a 13 (1101b) globalssdasel2gl[1]sdasel2gl[ 0] sdasel1gl[1]sdasel1gl[0]encbpgltxckselgltxrateg l fglen1 n/a 14 (1110b) globald rfengl rxpllpdglrxbistgl txbistgl oe2gl oe1gl pabrstg l fglen2 n/a 15 (1111b) mask d d7 d6 d5 d4 d3 d2 d1 d0 11111111
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 23 of 43 table 11.receive character status bits rxstx[2:0]priority description normal status receive bist status (receive bist = enabled) 000 7 normal character received .the valid data character on the output bus meets all the formatting requirements of data characters listed in table15 . bist data compare . character compared correctly. 001 7 special code detected . the valid special character on the output bus meets all the formatting requirements of special code characters listed in table16 , but is not the presently selected framing character or a decoder violation indication. bist command compare . character compared correctly. 010 2 receive elasticity buffer underrun/overrun error .the receive buffer was not able to add/drop a k28.5 or framing character bist last good . last character of bist sequence detected and valid. 011 5 framing character detected . this indicates that a character matching the patterns identified as a framing character (as selected by framcharx) was detected. the decoded value of this character is present in the associated output bus. 100 4 codeword violation . the character on the output bus is a c0.7. this indicates that the received character cannot be decoded into any valid character. bist last bad .last character of bist sequence detected invalid. 101 1 loss of sync .this indicates a pll out of lock condition bist start . receive bist is enabled on this channel, but character compares have not yet commenced. this also indicates a pll out of lock condition, and elasticity buffer overflow/underflow conditions. 110 6 running disparity error . the character on the output bus is a c4.7, c1.7, or c2.7. bist error . while comparing characters, a mismatch was found in one or more of the decoded character bits. 111 3 reserved bist wait . the receiver is comparing characters. but has not yet found the start of bist character to enable the lfsr.
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 24 of 43 receive bist detected low monitor data received rxstx = bist_start (101) no rx pll out of lock yes, rxstx = bist_data_compare (000) / bist_command_compare (001) compare next character auto-abort condition mismatch end-of-bist state yes, rxstx = bist_last_bad (100) yes no no, rxstx = bist_error (110) data or command match command rxstx = bist_command_compare (001) end-of-bist state data yes, rxstx = bist_last_good (010) no rxstx = bist_data_compare (000) figure 2. receive bist state machine elasticity buffer error start of bist detected rxstx = bist_wait (111) yes rxstx = bist_start (101) no
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 25 of 43 maximum ratings above which the useful life may be impaired. user guidelines only, not tested storage temperature.................................. C 65 c to +150 c ambient temperature with power applied............................................. C 55 c to +125 c supply voltage to ground potential............... C 0.5v to +3.8v dc voltage applied to lvttl outputs in high-z state....................................... C 0.5v to v cc + 0.5v output current into lvttl outputs (low)..................60 ma dc input voltage.................................... C 0.5v to v cc + 0.5v static discharge voltage..........................................> 2000 v (per mil-std-883, method 3015) latch-up current.....................................................> 200 ma power-up requirements the cyp(v)15g0403dxb requires one power-supply. the voltage on any input or i/o pin cannot exceed the power pin during power-up. operating range range ambient temperature v cc commercial 0 c to +70 c +3.3v 5% industrial C 40 c to +85 c +3.3v 5% cyp(v) 15g0403dxb dc electrical characteristics parameter description test conditions min. max. unit lvttl-compatible outputs v oht output high voltage i oh = 4 ma, v cc = min. 2.4 v v olt output low voltage i ol = 4 ma, v cc = min. 0.4 v i ost output short circuit current v out = 0v [10] , v cc = 3.3v C 20 C 100 ma i ozl high-z output leakage current v out = 0v, v cc C 20 20 a lvttl-compatible inputs v iht input high voltage 2.0 v cc + 0.3 v v ilt input low voltage C 0.5 0.8 v i iht input high current refclkx input, v in = v cc 1.5 ma other inputs, v in = v cc +40 a i ilt input low current refclkx input, v in = 0.0v C 1.5 ma other inputs, v in = 0.0v C 40 a i ihpdt input high current with internal pull-downv in = v cc +200 a i ilput input low current with internal pull-up v in = 0.0v C 200 a lvdiff inputs: refclkx v diff [11] input differential voltage 400 v cc mv v ihhp highest input high voltage 1.2 v cc v v illp lowest input low voltage 0.0 v cc /2 v v comref [12] common mode range 1.0 v cc C 1.2v v 3-level inputs v ihh three-level input high voltage min. v cc max. 0.87 * v cc v cc v v imm three-level input mid voltage min. v cc max. 0.47 * v cc 0.53 * v cc v v ill three-level input low voltage min. v cc max. 0.0 0.13 * v cc v i ihh input high current v in = v cc 200 a i imm input mid current v in = v cc /2 C 50 50 a i ill input low current v in = gnd C 200 a differential cml serial outputs: outa1 , outa2 , outb1 , outb2 outc1 , outc2 , outd1 , outd2 v ohc output high voltage (v cc referenced) 100 differential load v cc C 0.5 v cc C 0.2 v 150 differential load v cc C 0.5 v cc C 0.2 v 10.tested one output at a time, output shorted for less than one second, less than 10% duty cycle. 11.this is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. a logic-1 exists when the true (+) input is more positive than the complement ( ) input. a logic-0 exists when the complement ( ) input is more positive than true (+) input. 12.the common mode range defines the allowable range of refclkx+ and refclkx when refclkx+=refclkx . this marks the zero-crossing between the true and complement inputs as the signal switches between a logic-1 and a logic-0.
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 26 of 43 v olc output low voltage (v cc referenced) 100 differential load v cc C 1.4v cc C 0.7 v 150 differential load v cc C 1.4 v cc C 0.7 v v odif output differential voltage |(out+) (out )| 100 differential load 450 900 mv 150 differential load 560 1000 mv differential serial line receiver inputs: ina1 , ina2 , inb1 , inb2 , inc1 , inc2 , ind1 , ind2 v diffs [11] input differential voltage |(in+) (in )| 100 1200 mv v ihe highest input high voltage v cc v v ile lowest input low voltage v cc C 2.0 v i ihe input high current v in = v ihe max. 1350 a i ile input low current v in = v ile min. C 700 a vi com [13] common mode input range ((v cc C 2.0v)+0.5)min, (v cc C 0.5v) max. +1.25 +3.1 v power supply typ. max. i cc [14,15] max power supply current refclkx = max commercial 910 1270 ma industrial 1320 ma i cc [14,15] typical power supply current refclkx = 125 mhz commercial 900 1270 ma industrial 1320 ma cyp(v) 15g0403dxb dc electrical characteristics (continued) parameterdescriptiontest conditionsmin.max.unit ac test loads and waveforms 2.0v 0.8v gnd 2.0v 0.8v 80% 20% 80% 20% r l (includes fixture and probe capacitance) 3.0v v th =1.4v 270ps 270ps note 17 v th =1.4v 3.3v r1 r2 r1=590 r2=435 (includes fixture and probe capacitance) c l 7 pf (a) lvttl output test load r l =100 (b) cml output test load c l (c) lvttl input test waveform (d) cml/lvpecl input test waveform 1ns 1 ns v ihe v ile v ihe v ile note 16 note 16 cyp(v)15g0403dxb ac electrical characteristics parameter description min. maxunit cyp(v)15g0403dxb transmitter lvttl switching characteristics over the operating range f ts txclkx clock cycle frequency 19.5 150mhz t txclk txclkx period=1/f ts 6.66 51.28ns t txclkh [18] txclkx high time 2.2 ns t txclkl [18] txclkx low time 2.2 ns notes: 13.the common mode range defines the allowable range of input+ and input when input+=input . this marks the zero-crossing between the true and complement inputs as the signal switches between a logic-1 and a logic-0. 14.maximum i cc is measured with v cc = max, rfenx = 0,t a = 25 c, with all channels and serial line drivers enabled, sending a continuous alternating 01 pattern, and outputs unloaded. 15.typical i cc is measured under similar conditions except with v cc = 3.3v, t a = 25 c, rfenx = 0, with all channels enabled and one serial line driver per transmit channel sending a continuous alternating 01 pattern. the redundant outputs on each channel are powered down and the parallel outputs are unloaded. 16.cypress uses constant current (ate) load configurations and forcing functions. this figure is for reference only. 17.the lvttl switching threshold is 1.4v. all timing references are made relative to where the signal edges cross the threshold voltage. 18.tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 27 of 43 t txclkr [18,19,20,21] txclkx rise time 0.2 1.7 ns t txclkf [18,19,20,21] txclkx fall time 0.2 1.7 ns t txds transmit data set-up time to txclkx (txckselx 0) 2.2 ns t txdh transmit data hold time from txclkx (txckselx 0) 0.8 ns f tos txclkox clock frequency = 1x or 2x refclkx frequency 19.5 150mhz t txclko txclkox period=1/f tos 6.66 51.28ns t txclkod txclko duty cycle centered at 60% high time -1.9 0 ns cyp(v)15g0403dxb receiver lvttl switching characteristics over the operating range f rs rxclkx clock output frequency 9.75 150mhz t rxclkp rxclkx period = 1/f rs 6.66 102.5 6 ns t rxclkd rxclkx duty cycle centered at 50% (full rate and half rate when rxckselx = 0) C 1.0 +1.0ns t rxclkr [18] rxclkx rise time 0.3 1.2 ns t rxclkf [18] rxclkx fall time 0.3 1.2 ns t rxdv C [22] status and data valid time to rxclkx (rxratex = 0, rxckselx = 0) (full rate) 5ui C 1.8 [23] ns status and data valid time to rxclkx (rxratex = 1, rxckselx = 0) (half rate) 5ui C 1.3 [23] ns t rxdv+ [22] status and data valid time to rxclkx (rxratex = 0, rxckselx = 0) (full rate) 5ui C 1.7 [23] ns status and data valid time to rxclkx (rxratex = 1, rxckselx =0) (half rate) 5ui C 2.1 [23] ns cyp(v)15g0403dxb refclkx switching characteristics over the operating range f ref refclkx clock frequency 19.5 150mhz t refclk refclkx period = 1/f ref 6.6 51.28ns t refh refclkx high time (txratex = 1)(half rate) 5.9 [24] ns refclkx high time (txratex = 0)(full rate) 2.9 [18] ns t refl refclkx low time (txratex = 1)(half rate) 5.9 [24] ns refclkx low time (txratex = 0)(full rate) 2.9 [18] ns t refd [25] refclkx duty cycle 30 70 % t refr [18,19,20,21] refclkx rise time (20% C 80%) 2 ns t reff [18,19,20,21] refclkx fall time (20% C 80%) 2 ns t trefds transmit data set-up time to refclkx - full rate (txratex = 0, txckselx 1) 2.2 ns transmit data set-up time to refclkx - half rate (txratex = 1, txckselx 1) 1.9 ns t trefdh transmit data hold time from refclkx - full rate (txratex = 0, txckselx 1) 0.8 ns transmit data hold time from refclkx - half rate (txratex = 1, txckselx 1) 1.5 ns t rrefdw receive data valid time window (rxckselx 1) 10ui-5.8 ns notes: 19.the ratio of rise time to falling time must not vary by greater than 2:1. 20.for a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time. 21.all transmit ac timing parameters measured with 1ns typical rise time and fall time. 22.parallel data output specifications are only valid if all outputs are loaded with similar dc and ac loads. 23.receiver ui (unit interval) is calculated as 1/(f ref *20) (when txratex = 1) or 1/(f ref *10) (when txratex = 0). in an operating link this is equivalent to t b . 24.if refclkx is selected as receive interface clock (rxckselx=1), then this parameter has to be greater than or equal to 6.3 ns. 25.the duty cycle specification is a simultaneous condition with the t refh and t refl parameters. this means that at faster character rates the refclkx duty cycle cannot be as large as 30% C 70%.l. cyp(v)15g0403dxb ac electrical characteristics (continued) parameterdescriptionmin.maxunit
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 28 of 43 t rrefda receive data access time to refclkx (rxckselx 1) 9.7 [26] ns t refxdv C received data valid time to rxclk when rxckselx 1 (txratex = 0, rxratex = 0) 10ui [23] C 5.86 ns received data valid time to rxclk when rxckselx 1 (txratex = 0, rxratex = 1) 5ui - 2.43 [27] ns received data valid time to rxclk when rxckselx 1 (txratex = 1)10ui - 5.76 [27] ns t refxdv+ received data valid time from rxclk when rxckselx 1 (txratex = 0, rxratex = 0) 1.5 ns received data valid time from rxclk when rxckselx 1 (txratex = 0, rxratex = 1) 5ui- 1.83 [27] ns received data valid time from rxclk when rxckselx 1 (txratex = 1) 1.5 [27] ns t refrx [28] refclkx frequency referenced to received clock period C 0.15 +0.15% cyp(v)15g0403dxb bus configuration write timing characteristics over the operating range t datah bus configuration data hold 0 ns t datas bus configuration data setup 10 ns t wrenp bus configuration wren pulse width 10 ns cyp(v)15g0403dxb jtag test clock characteristics over the operating range f tclk jtag test clock frequency 20mhz t tclk jtag test clock period 50 ns cyp(v)15g0403dxb device reset characteristics over the operating range t rst device reset pulse width 30 ns cyp(v)15g0403dxb transmit serial outputs and tx pll characteristics over the operating range parameter description condition min. max.unit t b bit time 5128 660 ps t rise [18] cml output rise time 20 80% (cml test load) spdselx = high 50 270 ps spdselx = mid 100 500 ps spdselx =low 180 1000ps t fall [18] cml output fall time 80 20% (cml test load) spdselx = high 50 270 ps spdselx = mid 100 500 ps spdselx =low 180 1000ps t dj [18,29,31] deterministic jitter (peak-peak) [32] ieee 802.3z 27 ps t rj [18,30,31] random jitter ( ) [32] ieee 802.3z 11 ps t refj [18] refclkx jitter tolerance / phase noise limits tbd t txlock transmit pllx lock to refclkx 200 s notes: 26.since this timing parameter is greater than the minimum time period of refclk it sets an upper limit to the frequency in which refclkx can be used to clock the receive data out of the output register. for predictable timing, users can use this parameter only if refclk period is greater than sum of t rrefda and set- up time of the upstream device. when this condition is not true, rxclkx (a buffered or divided version of refclk when rxckselx = 1) could be used to clock the receive data out of the device. 27.measured using a 50% duty cycle reference clock 28.refclkx has no phase or frequency relationship with the recovered clock and only acts as a centering reference to reduce clock synchronization time. refclkx must be within 1500 ppm ( 0.15%) of the remote transmitter s pll reference (refclkx) frequency. although transmitting to a hotlink ii receiver channel necessitates the frequency difference between the transmitter and receiver reference clocks to be within 1500-ppm, the stability of the crystal needs to be within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard. for example, to be ieee 802.3z gigabit ethernet compliant, the frequency stability of the crystal needs to be within 100 ppm.l. 29.while sending continuous k28.5s, outputs loaded to a balanced 100 load, measured at the cross point of differential outputs, over the operating range. 30.while sending continuous k28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to refclkx input, over the operating range. 31.total jitter is calculated at an assumed ber of 1e 12. hence: total jitter (t j ) = (t rj * 14) + t dj . cyp(v)15g0403dxb receive serial inputs and cdr pll characteristics over the operating range cyp(v)15g0403dxb ac electrical characteristics (continued) parameterdescriptionmin.maxunit
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 29 of 43 t rxlock receive pll lock to input data stream (cold start) 376kui receive pll lock to input data stream 376kui t rxunlock receive pll unlock rate 46 ui t jtol [18] total jitter tolerance [32] ieee 802.3z 600 ps t djtol [18] deterministic jitter tolerance [32] ieee 802.3z 370 ps capacitance [18] parameter description test conditions max. unit c inttl ttl input capacitance t a = 25 c, f 0 = 1 mhz, v cc = 3.3v 7 pf c inpecl pecl input capacitance t a = 25 c, f 0 = 1 mhz, v cc = 3.3v 4 pf notes: 32.also meets all jitter generation and jitter tolerance requirements as specified by smpte 259, smpte 292, escon, ficon, fibre channel, and dvb-asi. cyp(v)15g0403dxb ac electrical characteristics (continued) parameterdescriptionmin.maxunit
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 30 of 43 cyp(v)15g0403dxb hotlink ii transmitter switching waveforms notes: 33.when refclkx is configured for half-rate operation (txrate = 1) and data is captured using refclkx instead of a txclkx clock. data is captured using both the rising and falling edges of refclkx. 34.the txclkox output remains at the character rate regardless of the state of txrate and does not follow the duty cycle of refclkx . 35.the rising edge of txclkox output has no direct phase relationship to the refclkx input. txclkx txdx[7:0], txctx[1:0], t txdh t txds t txclk t txclkh t txclkl transmit interface write timing txclkx selected refclkx transmit interface t refclk t refh t refl t trefds t trefdh write timing txratex = 0 txdx[7:0], txctx[1:0], refclkx selected t trefdh transmit interface write timing txratex = 1 refclkx t refclk t refl t refh note 33 txdx[7:0], txctx[1:0], t trefds t trefds t trefdh refclkx selected txclkox t txclko transmit interface txclkox timing txratex = 1 (internal) refclkx t refclk t refl t refh note 34 note 35
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 31 of 43 cyp(v)15g0403dxb hotlink ii transmitter switching waveforms (continued) txclkox t txclko t txoh t txol transmit interface txclkox timing refclkx note34 note35 t refclk t refh t refl txratex = 0 switching waveforms for the cyp(v)15g0403dxb hotlink ii receiver note: 36.when operated with a half-rate refclkx , the setup and hold specifications for data relative to rxclkx are relative to both rising and falling edges of the respective clock output 37.txerrx is synchronous to rxclkx only when rxclkx is selected as refclk. refclkx rxdx[7:0], rxstx[2:0], t refclk t refh t refl receive interface read timing full-rate rxclkx rxclkx t refxdv+ t refxdv C t rrefda refclkx selected t rrefdw t rrefdw txerrx [ 37 ] refclkx rxdx[7:0], rxstx[2:0], t refclk t refh t refl receive interface read timing half-rate rxclkx t rrefda rxclkx t refxdv+ t refxdv C note 36 t rrefda refclkx selected t rrefdw t rrefdw txerrx [ 37 ]
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 32 of 43 switching waveforms for the cyp(v)15g0403dxb hotlink ii receiver rxclkx+ rxdx[7:0], rxstx[2:0], t rxdv+ t rxclkp receive interface read timing rxratex = 0 rxclkx- t rxdv C recovered clock selected rxclkx+ rxdx[7:0], rxstx[2:0] t rxdv+ t rxdv C t rxclkp receive interface read timing rxratex = 1 rxclkx- recovered clock selected addr[3:0] t datas bus configuration write timing data[7:0] wren t datah t wrenp
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 33 of 43 table 12.package coordinate signal allocation ball id signal name signal type ball id signal name signal type ball id signal name signal type a01 inc1 C cml in c07 ulcc lvttl in pu f17 nc no connect a02 outc1 C cml out c08 gnd ground f18 rxstb[1] lvttl out a03 inc2 C cml in c09 data[7] lvttl in pu f19 txclkob lvttl out a04 outc2 C cml out c10 data[5] lvttl in pu f20 rxstb[0] lvttl out a05 vcc power c11 data[3] lvttl in pu g01 txdc[7] lvttl in a06 ind1 C cml in c12 data[1] lvttl in pu g02 wren lvttl in pu a07 outd1 C cml out c13 gnd ground g03 txdc[4] lvttl in a08 gnd ground c14 nc no connect g04 txdc[1] lvttl in a09 ind2 C cml in c15 spdseld 3-level sel g17 spdselb 3-level sel a10 outd2 C cml out c16 vcc power g18 lpenc lvttl in pd a11 ina1 C cml in c17 ldtden lvttl in pu g19 spdsela 3-level sel a12 outa1 C cml out c18 trst lvttl in pu g20 rxdb[1] lvttl out a13 gnd ground c19 lpend lvttl in pd h01 gnd ground a14 ina2 C cml in c20 tdo lvttl 3-s out h02 gnd ground a15 outa2 C cml out d01 tclk lvttl in pd h03 gnd ground a16 vcc power d02 reset lvttl in pu h04 gnd ground a17 inb1 C cml in d03 inseld lvttl in h17 gnd ground a18 outb1 C cml out d04 insela lvttl in h18 gnd ground a19 inb2 C cml in d05 vcc power h19 gnd ground a20 outb2 C cml out d06 ulca lvttl in pu h20 gnd ground b01 inc1+ cml in d07 spdselc 3-level sel j01 txctc[1] lvttl in b02 outc1+ cml out d08 gnd ground j02 txdc[5] lvttl in b03 inc2+ cml in d09 data[6] lvttl in pu j03 txdc[2] lvttl in b04 outc2+ cml out d10 data[4] lvttl in pu j04 txdc[3] lvttl in b05 vcc power d11 data[2] lvttl in pu j17 rxstb[2] lvttl out b06 ind1+ cml in d12 data[0] lvttl in pu j18 rxdb[0] lvttl out b07 outd1+ cml out d13 gnd ground j19 rxdb[5] lvttl out b08 gnd ground d14 lpenb lvttl in pd j20 rxdb[2] lvttl out b09 ind2+ cml in d15 ulcb lvttl in pu k01 rxdc[2] lvttl out b10 outd2+ cml out d16 vcc power k02 refclkc C pecl in b11 ina1+ cml in d17 lpena lvttl in pd k03 txctc[0] lvttl in b12 outa1+ cml out d18 lten1 lvttl in pd k04 txclkc lvttl in pd b13 gnd ground d19 scanen2 lvttl in pd k17 rxdb[3] lvttl out b14 ina2+ cml in d20 tmen3 lvttl in pd k18 rxdb[4] lvttl out b15 outa2+ cml out e01 vcc power k19 rxdb[7] lvttl out b16 vcc power e02 vcc power k20 lfib lvttl out b17 inb1+ cml in e03 vcc power l01 rxdc[3] lvttl out b18 outb1+ cml out e04 vcc power l02 refclkc+ pecl in b19 inb2+ cml in e17 vcc power l03 lfic lvttl out b20 outb2+ cml out e18 vcc power l04 txdc[6] lvttl in c01 tdi lvttl in pu e19 vcc power l17 rxdb[6] lvttl out c02 tms lvttl in pu e20 vcc power l18 rxclkb+ lvttl out c03 inselc lvttl in f01 rxdc[6] lvttl out l19 rxclkb C lvttl out c04 inselb lvttl in f02 rxdc[7] lvttl out l20 txdb[6] lvttl in c05 vcc power f03 txdc[0] lvttl in m01 rxdc[4] lvttl out c06 ulcd lvttl in pu f04 nc no connect m02 rxdc[5] lvttl out
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 34 of 43 m03 nc no connect u03 txdd[2] lvttl in w03 lfid lvttl out m04 txerrc lvttl out u04 txctd[1] lvttl in w04 rxclkd C lvttl out m17refclkb+ pecl in u05 vcc power w05 vcc power m18refclkb C pecl in u06 rxdd[2] lvttl out w06 rxdd[4] lvttl out m19 txerrb lvttl out u07 rxdd[1] lvttl out w07 rxstd[1] lvttl out m20 txclkb lvttl in pd u08 gnd ground w08 gnd ground n01 gnd ground u09 txcta[1] lvttl in w09 addr [3] lvttl in pu n02 gnd ground u10 addr [0] lvttl in pu w10 addr [1] lvttl in pu n03 gnd ground u11 refclkd C pecl in w11 rxclka+ lvttl out n04 gnd ground u12 txda[1] lvttl in w12 txerra lvttl out n17 gnd ground u13 gnd ground w13 gnd ground n18 gnd ground u14 txda[4] lvttl in w14 txda[2] lvttl in n19 gnd ground u15 txcta[0] lvttl in w15 txda[6] lvttl in n20 gnd ground u16 vcc power w16 vcc power p01 rxdc[1] lvttl out u17 rxda[2] lvttl out w17 lfia lvttl out p02 rxdc[0] lvttl out u18 txctb[0] lvttl in w18refclka+ pecl in p03 rxstc[0] lvttl out u19 rxsta[2] lvttl out w19 rxda[4] lvttl out p04 rxstc[1] lvttl out u20 rxsta[1] lvttl out w20 rxda[1] lvttl out p17 txdb[5] lvttl in v01 txdd[3] lvttl in y01 txdd[6] lvttl in p18 txdb[4] lvttl in v02 txdd[4] lvttl in y02 txclkd lvttl in pd p19 txdb[3] lvttl in v03 txctd[0] lvttl in y03 rxdd[7] lvttl out p20 txdb[2] lvttl in v04 rxdd[6] lvttl out y04 rxclkd+ lvttl out r01 rxstc[2] lvttl out v05 vcc power y05 vcc power r02 txclkoc lvttl out v06 rxdd[3] lvttl out y06 rxdd[5] lvttl out r03 rxclkc+ lvttl out v07 rxstd[0] lvttl out y07 rxdd[0] lvttl out r04 rxclkc C lvttl out v08 gnd ground y08 gnd ground r17 txdb[1] lvttl in v09 rxstd[2] lvttl out y09 txclkod lvttl out r18 txdb[0] lvttl in v10 addr [2] lvttl in pu y10 nc no connect r19 txctb[1] lvttl in v11 refclkd+ pecl in y11 txclka lvttl in pd r20 txdb[7] lvttl in v12 txclkoa lvttl out y12 rxclka C lvttl out t01 vcc power v13 gnd ground y13 gnd ground t02 vcc power v14 txda[3] lvttl in y14 txda[0] lvttl in t03 vcc power v15 txda[7] lvttl in y15 txda[5] lvttl in t04 vcc power v16 vcc power y16 vcc power t17 vcc power v17 rxda[7] lvttl out y17 txerrd lvttl out t18 vcc power v18 rxda[3] lvttl out y18 refclka C pecl in t19 vcc power v19 rxda[0] lvttl out y19 rxda[6] lvttl out t20 vcc power v20 rxsta[0] lvttl out y20 rxda[5] lvttl out u01 txdd[0] lvttl in w01 txdd[5] lvttl in u02 txdd[1] lvttl in w02 txdd[7] lvttl in table 12. package coordinate signal allocation (continued) ball idsignal namesignal type ball idsignal namesignal type ball idsignal namesignal type
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 35 of 43 x3.230 codes and notation conventions information transmitted over a serial link is encoded eight bits at a time into a 10-bit transmission character and then sent serially, bit by bit. information received over a serial link is collected ten bits at a time, and those transmission characters that are used for data characters are decoded into the correct eight-bit codes. the 10-bit transmission code supports all 256 8-bit combinations. some of the remaining transmission characters (special characters) are used for functions other than data transmission. the primary use of a transmission code is to improve the transmission characteristics of a serial link. the encoding defined by the transmission code ensures that sufficient transitions are present in the serial bit stream to make clock recovery possible at the receiver. such encoding also greatly increases the likelihood of detecting any single or multiple bit errors that may occur during transmission and reception of information. in addition, some special characters of the trans- mission code selected by fibre channel standard contain a distinct and easily recognizable bit pattern that assists the receiver in achieving character alignment on the incoming bit stream. notation conventions the documentation for the 8b/10b transmission code uses letter notation for the bits in an 8-bit byte. fibre channel standard notation uses a bit notation of a, b, c, d, e, f, g, h for the 8-bit byte for the raw 8-bit data, and the letters a, b, c, d, e, i, f, g, h, j for encoded 10-bit data. there is a correspon- dence between bit a and bit a, b and b, c and c, d and d, e and e, f and f, g and g, and h and h. bits i and j are derived, respectively, from (a,b,c,d,e) and (f,g,h). the bit labeled a in the description of the 8b/10b transmission code corresponds to bit 0 in the numbering scheme of the fc- 2 specification, b corresponds to bit 1, as shown below. fc-2 bit designation 76543210 hotlink d/q designation 76543210 8b/10b bit designation hgfedcba to clarify this correspondence, the following example shows the conversion from an fc-2 valid data byte to a transmission character. fc-245h bits: 7654 3210 0100 0101 converted to 8b/10b notation, note that the order of bits has been reversed): data byte named5.2 bits: abcde fgh 10100 010 translated to a transmission character in the 8b/10b trans- mission code: bits: abcdei fghj 101001 0101 each valid transmission character of the 8b/10b trans- mission code has been given a name using the following convention: cxx.y, where c is used to show whether the trans- mission character is a data character (c is set to d, and sc/d = low) or a special character (c is set to k, and sc/d = high). when c is set to d, xx is the decimal value of the binary number composed of the bits e, d, c, b, and a in that order, and the y is the decimal value of the binary number composed of the bits h, g, and f in that order. when c is set to k, xx and y are derived by comparing the encoded bit patterns of the special character to those patterns derived from encoded valid data bytes and selecting the names of the patterns most similar to the encoded bit patterns of the special character. under the above conventions, the transmission character used for the examples above, is referred to by the name d5.2. the special character k29.7 is so named because the first six bits (abcdei) of this character make up a bit pattern similar to that resulting from the encoding of the unencoded 11101 pattern (29), and because the second four bits (fghj) make up a bit pattern similar to that resulting from the encoding of the unencoded 111 pattern (7). note . this definition of the 10-bit transmission code is based on the following references, which describe the same 10-bit transmission code. a.x. widmer and p.a. franaszek. a dc-balanced, parti- tioned-block, 8b/10b transmission code ibm journal of research and development, 27, no. 5: 440-451 (september, 1983). u.s. patent 4,486,739. peter a. franaszek and albert x. widmer. byte-oriented dc balanced (0.4) 8b/10b parti- tioned block transmission code (december 4, 1984). fibre channel physical and signaling interface (ans x3.230- 1994 ansi fc-ph standard). ibm enterprise systems architecture/390 escon i/o interface (document number sa22-7202). 8b/10b transmission code the following information describes how the tables are used for both generating valid transmission characters (encoding) and checking the validity of received transmission characters (decoding). it also specifies the ordering rules followed when transmitting the bits within a character and the characters within any higher-level constructs specified by a standard. transmission order within the definition of the 8b/10b transmission code, the bit positions of the transmission characters are labeled a, b, c, d, e, i, f, g, h, j. bit a is transmitted first followed by bits b, c, d, e, i, f, g, h, and j in that order. note that bit i is transmitted between bit e and bit f, rather than in alphabetical order. valid and invalid transmission characters the following tables define the valid data characters and valid special characters (k characters), respectively. the tables are used for both generating valid transmission characters and checking the validity of received transmission characters. in the tables, each valid-data-byte or special- character-code entry has two columns that represent two transmission characters. the two columns correspond to the current value of the running disparity. running disparity is a binary parameter with either a negative ( C ) or positive (+) value. after powering on, the transmitter may assume either a positive or negative value for its initial running disparity. upon transmission of any transmission character, the transmitter selects the proper version of the transmission character
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 36 of 43 based on the current running disparity value, and the trans- mitter calculates a new value for its running disparity based on the contents of the transmitted character. special character codes c1.7 and c2.7 can be used to force the transmission of a specific special character with a specific running disparity as required for some special sequences in x3.230. after powering on, the receiver may assume either a positive or negative value for its initial running disparity. upon reception of any transmission character, the receiver decides whether the transmission character is valid or invalid according to the following rules and tables and calculates a new value for its running disparity based on the contents of the received character. the following rules for running disparity are used to calculate the new running-disparity value for transmission characters that have been transmitted and received. running disparity for a transmission character is calculated from sub-blocks, where the first six bits (abcdei) form one sub- block and the second four bits (fghj) form the other sub-block. running disparity at the beginning of the 6-bit sub-block is the running disparity at the end of the previous transmission character. running disparity at the beginning of the 4-bit sub- block is the running disparity at the end of the 6-bit sub-block. running disparity at the end of the transmission character is the running disparity at the end of the 4-bit sub-block. running disparity for the sub-blocks is calculated as follows: 1.running disparity at the end of any sub-block is positive if the sub-block contains more ones than zeros. it is also positive at the end of the 6-bit sub-block if the 6-bit sub- block is 000111, and it is positive at the end of the 4-bit sub- block if the 4-bit sub-block is 0011. 2.running disparity at the end of any sub-block is negative if the sub-block contains more zeros than ones. it is also negative at the end of the 6-bit sub-block if the 6-bit sub- block is 111000, and it is negative at the end of the 4-bit sub- block if the 4-bit sub-block is 1100. 3.otherwise, running disparity at the end of the sub-block is the same as at the beginning of the sub-block. use of the tables for generating transmission characters the appropriate entry in table15 for the valid data byte or table16 for special character byte identify which trans- mission character is generated. the current value of the transmitter s running disparity is used to select the trans- mission character from its corresponding column. for each transmission character transmitted, a new value of the running disparity is calculated. this new value is used as the transmitter s current running disparity for the next valid data byte or special character byte encoded and transmitted. table13 shows naming notations and examples of valid trans- mission characters. use of the tables for checking the validity of received transmission characters the column corresponding to the current value of the receiver s running disparity is searched for the received transmission character. if the received transmission character is found in the proper column, then the trans- mission character is valid and the associated data byte or special character code is determined (decoded). if the received transmission character is not found in that column, then the transmission character is invalid. this is called a code violation. independent of the transmission character s validity, the received transmission character is used to calculate a new value of running disparity. the new value is used as the receiver s current running disparity for the next received transmission character. detection of a code violation does not necessarily show that the transmission character in which the code violation was detected is in error. code violations may result from a prior error that altered the running disparity of the bit stream which did not result in a detectable error at the transmission character in which the error occurred. table14 shows an example of this behavior. table 13.valid transmission characters data byte name d in or q out hex value 765 43210 d0.0 00000000 00 d1.0 00000001 01 d2.0 00000010 02 . . . . . . . . d5.2 01000101 45 . . . . . . . . d30.7 11111110 fe d31.7 11111111 ff table 14.code violations resulting from prior errors rd character rd character rd character rd transmitted data character C d21.1 C d10.2 C d23.5 + transmitted bit stream C 101010 1001 C 010101 0101 C 111010 1010 + bit stream after error C 101010 1011 + 010101 0101 + 111010 1010 + decoded data character C d21.0 + d10.2 + code violation +
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 37 of 43 table 15.valid data characters (txctx[0] = 0, rxstx[2:0] = 000) data byte name bits current rd current rd+ data byte name bits current rd current rd+ hgfedcba abcdeifghj abcdeifghj hgfedcba abcdeifghj abcdeifghj d0.00000000010011101000110001011d0.10010000010011110010110001001 d1.00000000101110101001000101011d1.10010000101110110011000101001 d2.00000001010110101000100101011d2.10010001010110110010100101001 d3.00000001111000110111100010100d3.10010001111000110011100011001 d4.00000010011010101000010101011d4.10010010011010110010010101001 d5.00000010110100110111010010100d5.10010010110100110011010011001 d6.00000011001100110110110010100d6.10010011001100110010110011001 d7.00000011111100010110001110100d7.10010011111100010010001111001 d8.00000100011100101000001101011d8.10010100011100110010001101001 d9.00000100110010110111001010100d9.10010100110010110011001011001 d10.00000101001010110110101010100d10.10010101001010110010101011001 d11.00000101111010010111101000100d11.10010101111010010011101001001 d12.00000110000110110110011010100d12.10010110000110110010011011001 d13.00000110110110010111011000100d13.10010110110110010011011001001 d14.00000111001110010110111000100d14.10010111001110010010111001001 d15.00000111101011101001010001011d15.10010111101011110011010001001 d16.00001000001101101001001001011d16.10011000001101110011001001001 d17.00001000110001110111000110100d17.10011000110001110011000111001 d18.00001001001001110110100110100d18.10011001001001110010100111001 d19.00001001111001010111100100100d19.10011001111001010011100101001 d20.00001010000101110110010110100d20.10011010000101110010010111001 d21.00001010110101010111010100100d21.10011010110101010011010101001 d22.00001011001101010110110100100d22.10011011001101010010110101001 d23.00001011111101001000001011011d23.10011011111101010010001011001 d24.00001100011001101000011001011d24.10011100011001110010011001001 d25.00001100110011010111001100100d25.10011100110011010011001101001 d26.00001101001011010110101100100d26.10011101001011010010101101001 d27.00001101111011001000010011011d27.10011101111011010010010011001 d28.00001110000111010110011100100d28.10011110000111010010011101001 d29.00001110110111001000100011011d29.10011110110111010010100011001 d30.00001111001111001001000011011d30.10011111001111010011000011001 d31.00001111110101101000101001011d31.10011111110101110010101001001
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 38 of 43 d0.20100000010011101010110000101d0.30110000010011100110110001100 d1.20100000101110101011000100101d1.30110000101110100111000101100 d2.20100001010110101010100100101d2.30110001010110100110100101100 d3.20100001111000101011100010101d3.30110001111000111001100010011 d4.20100010011010101010010100101d4.30110010011010100110010101100 d5.20100010110100101011010010101d5.30110010110100111001010010011 d6.20100011001100101010110010101d6.30110011001100111000110010011 d7.20100011111100001010001110101d7.30110011111100011000001110011 d8.20100100011100101010001100101d8.30110100011100100110001101100 d9.20100100110010101011001010101d9.30110100110010111001001010011 d10.20100101001010101010101010101d10.30110101001010111000101010011 d11.20100101111010001011101000101d11.30110101111010011001101000011 d12.20100110000110101010011010101d12.30110110000110111000011010011 d13.20100110110110001011011000101d13.30110110110110011001011000011 d14.20100111001110001010111000101d14.30110111001110011000111000011 d15.20100111101011101011010000101d15.30110111101011100111010001100 d16.20101000001101101011001000101d16.30111000001101100111001001100 d17.20101000110001101011000110101d17.30111000110001111001000110011 d18.20101001001001101010100110101d18.30111001001001111000100110011 d19.20101001111001001011100100101d19.30111001111001011001100100011 d20.20101010000101101010010110101d20.30111010000101111000010110011 d21.20101010110101001011010100101d21.30111010110101011001010100011 d22.20101011001101001010110100101d22.30111011001101011000110100011 d23.20101011111101001010001010101d23.30111011111101000110001011100 d24.20101100011001101010011000101d24.30111100011001100110011001100 d25.20101100110011001011001100101d25.30111100110011011001001100011 d26.20101101001011001010101100101d26.30111101001011011000101100011 d27.20101101111011001010010010101d27.30111101111011000110010011100 d28.20101110000111001010011100101d28.30111110000111011000011100011 d29.20101110110111001010100010101d29.30111110110111000110100011100 d30.20101111001111001011000010101d30.30111111001111000111000011100 d31.20101111110101101010101000101d31.30111111110101100110101001100 table 15. valid data characters (txctx[0] = 0, rxstx[2:0] = 000) (continued) data byte name bitscurrent rd current rd+ data byte name bitscurrent rd current rd+ hgf edcbaabcdei fghjabcdei fghj hgf edcbaabcdei fghjabcdei fghj
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 39 of 43 d0.41000000010011100100110001101d0.51010000010011110100110001010 d1.41000000101110100101000101101d1.51010000101110110101000101010 d2.41000001010110100100100101101d2.51010001010110110100100101010 d3.41000001111000111011100010010d3.51010001111000110101100011010 d4.41000010011010100100010101101d4.51010010011010110100010101010 d5.41000010110100111011010010010d5.51010010110100110101010011010 d6.41000011001100111010110010010d6.51010011001100110100110011010 d7.41000011111100011010001110010d7.51010011111100010100001111010 d8.41000100011100100100001101101d8.51010100011100110100001101010 d9.41000100110010111011001010010d9.51010100110010110101001011010 d10.41000101001010111010101010010d10.51010101001010110100101011010 d11.41000101111010011011101000010d11.51010101111010010101101001010 d12.41000110000110111010011010010d12.51010110000110110100011011010 d13.41000110110110011011011000010d13.51010110110110010101011001010 d14.41000111001110011010111000010d14.51010111001110010100111001010 d15.41000111101011100101010001101d15.51010111101011110101010001010 d16.41001000001101100101001001101d16.51011000001101110101001001010 d17.41001000110001111011000110010d17.51011000110001110101000111010 d18.41001001001001111010100110010d18.51011001001001110100100111010 d19.41001001111001011011100100010d19.51011001111001010101100101010 d20.41001010000101111010010110010d20.51011010000101110100010111010 d21.41001010110101011011010100010d21.51011010110101010101010101010 d22.41001011001101011010110100010d22.51011011001101010100110101010 d23.41001011111101000100001011101d23.51011011111101010100001011010 d24.41001100011001100100011001101d24.51011100011001110100011001010 d25.41001100110011011011001100010d25.51011100110011010101001101010 d26.41001101001011011010101100010d26.51011101001011010100101101010 d27.41001101111011000100010011101d27.51011101111011010100010011010 d28.41001110000111011010011100010d28.51011110000111010100011101010 d29.41001110110111000100100011101d29.51011110110111010100100011010 d30.41001111001111000101000011101d30.51011111001111010101000011010 d31.41001111110101100100101001101d31.51011111110101110100101001010 table 15. valid data characters (txctx[0] = 0, rxstx[2:0] = 000) (continued) data byte name bitscurrent rd current rd+ data byte name bitscurrent rd current rd+ hgf edcbaabcdei fghjabcdei fghj hgf edcbaabcdei fghjabcdei fghj
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 40 of 43 d0.61100000010011101100110000110d0.71110000010011100010110001110 d1.61100000101110101101000100110d1.71110000101110100011000101110 d2.61100001010110101100100100110d2.71110001010110100010100101110 d3.61100001111000101101100010110d3.71110001111000111101100010001 d4.61100010011010101100010100110d4.71110010011010100010010101110 d5.61100010110100101101010010110d5.71110010110100111101010010001 d6.61100011001100101100110010110d6.71110011001100111100110010001 d7.61100011111100001100001110110d7.71110011111100011100001110001 d8.61100100011100101100001100110d8.71110100011100100010001101110 d9.61100100110010101101001010110d9.71110100110010111101001010001 d10.61100101001010101100101010110d10.71110101001010111100101010001 d11.61100101111010001101101000110d11.71110101111010011101101001000 d12.61100110000110101100011010110d12.71110110000110111100011010001 d13.61100110110110001101011000110d13.71110110110110011101011001000 d14.61100111001110001100111000110d14.71110111001110011100111001000 d15.61100111101011101101010000110d15.71110111101011100011010001110 d16.61101000001101101101001000110d16.71111000001101100011001001110 d17.61101000110001101101000110110d17.71111000110001101111000110001 d18.61101001001001101100100110110d18.71111001001001101110100110001 d19.61101001111001001101100100110d19.71111001111001011101100100001 d20.61101010000101101100010110110d20.71111010000101101110010110001 d21.61101010110101001101010100110d21.71111010110101011101010100001 d22.61101011001101001100110100110d22.71111011001101011100110100001 d23.61101011111101001100001010110d23.71111011111101000010001011110 d24.61101100011001101100011000110d24.71111100011001100010011001110 d25.61101100110011001101001100110d25.71111100110011011101001100001 d26.61101101001011001100101100110d26.71111101001011011100101100001 d27.61101101111011001100010010110d27.71111101111011000010010011110 d28.61101110000111001100011100110d28.71111110000111011100011100001 d29.61101110110111001100100010110d29.71111110110111000010100011110 d30.61101111001111001101000010110d30.71111111001111000011000011110 d31.61101111110101101100101000110d31.71111111110101100010101001110 table 15. valid data characters (txctx[0] = 0, rxstx[2:0] = 000) (continued) data byte name bitscurrent rd current rd+ data byte name bitscurrent rd current rd+ hgf edcbaabcdei fghjabcdei fghj hgf edcbaabcdei fghjabcdei fghj
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 41 of 43 table 16.valid special character codes and sequences (txctx = special character code or rxstx[2:0] = 001) [38,39] s.c. code name s.c. byte name current rd abcdeifghj current rd+ abcdeifghj cypress alternate s.c. byte name [40] bits hgfedcba s.c. byte name [40] bits hgfedcba k28.0 c0.0(c00) 00000000 c28.0(c1c)000 11100 0011110100 1100001011 k28.1 [41] c1.0(c01) 00000001 c28.1(c3c)001 11100 0011111001 1100000110 k28.2 [41] c2.0(c02) 00000010 c28.2(c5c)010 11100 0011110101 1100001010 k28.3 c3.0(c03) 00000011 c28.3(c7c)011 11100 0011110011 1100001100 k28.4 [41] c4.0(c04) 00000100 c28.4(c9c)100 11100 0011110010 1100001101 k28.5 [41,42] c5.0(c05) 00000101 c28.5(cbc)101 11100 0011111010 1100000101 k28.6 [41] c6.0(c06) 00000110 c28.6(cdc)110 11100 0011110110 1100001001 k28.7 [41,43] c7.0(c07) 00000111 c28.7(cfc)111 11100 0011111000 1100000111 k23.7 c8.0(c08) 00001000 c23.7(cf7) 111 10111 1110101000 0001010111 k27.7 c9.0(c09) 00001001 c27.7(cfb)111 11011 1101101000 0010010111 k29.7 c10.0(c0a)00001010 c29.7(cfd)111 11101 1011101000 0100010111 k30.7 c11.0(c0b) 00001011 c30.7(cfe) 111 11110 0111101000 1000010111 end of frame sequence eofxx c2.1(c22) 00100010 c2.1 (c22)00100010 k28.5,dn.xxx0 [44] +k28.5,dn.xxx1 [44] code rule violation and svs tx pattern exception [43, 45] c0.7(ce0) 11100000 c0.7 (ce0)11100000 1001111000 0110000111 k28.5 [46] c1.7(ce1) 11100001 c1.7 (ce1)11100001 0011111010 0011111010 +k28.5 [47] c2.7(ce2) 11100010 c2.7 (ce2)11100010 1100000101 1100000101 running disparity violation pattern exception [48] c4.7(ce4) 11100100 c4.7 (ce4)11100100 1101110101 0010001010 ordering information speed ordering code package name package type operating range standard cyp(v)15g0403dxb-bgc bl256 256-ball thermally enhanced ball grid arraycommercial standard cyp(v)15g0403dxb-bgi bl256 256-ball thermally enhanced ball grid arrayindustrial notes: 38.all codes not shown are reserved. 39.notation for special character code name is consistent with fibre channel and escon naming conventions. special character code name is intended to describe binary information present on i/o pins. common usage for the name can either be in the form used for describing data patterns (i.e., c0.0 through c31.7), or in hex notation (i.e., cnn where nn = the specified value between 00 and ff). 40.both the cypress and alternate encodings may be used for data transmission to generate specific special character codes. the decoding process for received characters generates cypress codes or alternate codes as selected by the boe[7:0] configuration inputs. 41.these characters are used for control of escon interfaces. they can be sent as embedded commands or other markers when not operating using escon protocols. 42.the k28.5 character is used for framing operations by the receiver. it is also the pad or fill character transmitted to maintain the serial link when no user data is available. 43.care must be taken when using this special character code. when a c7.0 or a c0.7 is followed by a d11.x or d20.x, an alias k28.5 sync character is created. these sequences can cause erroneous framing and should be avoided while rfenx = 1. 44.c2.1 = transmit either C k28.5+ or +k28.5 C as determined by current rd and modify the transmission character that follows, by setting its least significant bit to 1 or 0. if current rd at the start of the following character is plus (+) the lsb is set to 0, and if current rd is minus ( C ) the lsb becomes 1. this modification allows construction of x3.230 eof frame delimiters wherein the second data byte is determined by the current rd. for example, to send eofdt the controller could issue the sequence c2.1 C d21.4 C d21.4 C d21.4, and the hotlink transmitter sends either k28.5 C d21.4 C d21.4 C d21.4 or k28.5 C d21.5 C d21.4 C d21.4 based on current rd. likewise to send eofdti the controller could issue the sequence c2.1 C d10.4 C d21.4 C d21.4, and the hotlink transmitter sends either k28.5 C d10.4 C d21.4 C d21.4 or k28.5 C d10.5 C d21.4 C d21.4 based on current rd. the receiver never outputs this special character, since k28.5 is decoded as c5.0, c1.7, or c2.7, and the subsequent bytes are decoded as data. 45.c0.7 = transmit a deliberate code rule violation. the code chosen for this function follows the normal running disparity rules. transmission of this special character has the same effect as asserting txsvs = high. the receiver only outputs this special character if the transmission character being decoded is not found in the tables. 46.c1.7 = transmit negative k28.5 ( k28.5+) disregarding current rd. the receiver only outputs this special character if k28.5 is received with the wrong running disparity. the receiver outputs c1.7 if k28.5 is received with rd+, otherwise k28.5 is decoded as c5.0 or c2.7. 47.c2.7 = transmit positive k28.5 (+k28.5 ) disregarding current rd. the receiver only outputs this special character if k28.5 is received with the wrong running disparity. the receiver outputs c2.7 if +k28.5 is received with rd , otherwise k28.5 is decoded as c5.0 or c1.7. 48.c4.7 = transmit a deliberate code rule violation to indicate a running disparity violation. the receiver only outputs this special character if the transmission character being decoded is found in the tables, but running disparity does not match. this might indicate that an error occurred in a prior byte.
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 42 of 43 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. ibm and escon are registered trademarks, and ficon is a trademark, of international business machines. hotlink is a registered trademark and hotlink ii and multiframe are trademarks of cypress semiconductor. all product and company names mentioned in this document may be the trademarks of their respective holders. package diagram 256-lead l2 ball grid array (27 x 27 x 1.57 mm) bl256 51-85123-*e
preliminary cyp15g0403dxb cyv15g0403dxb document #: 38-02065 rev. *c page 43 of 43 document history page document title: cyp(v)15g0403dxb independent clock quad hotlink ii ? transceiver (preliminary) document number: 38-02065 rev. ecn no. issue date orig. of change description of change ** 118422 09/24/02 lnm new data sheet *a 125289 04/04/03 cgx revised entire data sheet redefined device *b 128692 08/14/03 pds provided ac timing information for txerrx added additional information regarding the availability of half-rate rxclkx when refclkx is a full-rate clock with rxckselx = 1 added influence of ulcx input on lfix status added influence of decmodex on decoder bypass revised the text for device configuration and control interface for better clarity removed the timing parameter t rrefdv and added the timing parameter t rrefdw instead. this change was done to provide a more meaningful timing parameter revised t rrefda from 9.5 ns to 9.7 ns added additional information to device configuration strategy *c 234390 see ecn pds removed dependence of decmodex on decoder bypass. revised ac timing parameters (ac electrical characteristics) to match final device characterization. expanded the cdr range controller s permissible frequency offset between incoming serial signalling rate and reference clock from 200-ppm to 1500-ppm (changed parameter t refrx ).

▲Up To Search▲

Price & Availability of CYP15G0403DXB-BGC

	To Download CYP15G0403DXB-BGC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .